FinFET Contact Cavity Structure for Lower Parasitic Capacitance
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Solution Overview
Problem
The performance of fin field effect transistors (FinFETs) needs improvement due to challenges in manufacturing and design, particularly in controlling static electricity and reducing parasitic capacitance as device sizes shrink.
Innovation Solution
A semiconductor structure and fabrication method involving gate structures, source/drain plugs, and sacrificial spacers are formed on a base substrate, with cavities created between the gate structures and source/drain plugs, and a dielectric layer is applied to enclose the cavities, reducing parasitic capacitance and improving static electricity control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If device size is reduced to increase density, then device density and speed are improved, but parasitic capacitance increases and static electricity control deteriorates
Solution Approach 1:
The patent extracts the harmful dielectric material from the region between the gate structure and source/drain plugs by forming cavities (air gaps). This removes the source of parasitic capacitance while maintaining the necessary electrical connections, directly addressing the problem of increased parasitic capacitance due to device scaling.
Solution Approach 2:
The patent applies different dielectric properties to different regions: air (vacuum) in the cavity region to minimize capacitance, and conventional dielectric material in other regions for proper electrical isolation. This localized differentiation of material properties optimizes the structure for reduced parasitic capacitance while maintaining overall device functionality.
2Quantity of substance
If device size is reduced to increase density, then device density and speed are improved, but static electricity control deteriorates
Solution Approach 1:
By removing the dielectric material and forming air-filled cavities between the gate structure and source/drain plugs, the patent eliminates the medium that can support unwanted electrical fields and static charge accumulation, thereby improving static electricity control in scaled devices.
Solution Approach 2:
The patent creates regions with different electrical properties: the air cavity provides excellent electrical isolation and reduces capacitive coupling, while other regions maintain appropriate dielectric properties for electrical connectivity. This local differentiation improves electrostatic control.
3Object-affected harmful factors
If sacrificial spacers are removed to form cavities, then parasitic capacitance is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent forms sacrificial spacer structures during the fabrication process that are later removed to create the desired cavities. This preliminary action allows for precise cavity formation using standard fabrication techniques, managing manufacturing complexity through planned intermediate structures.
Solution Approach 2:
The sacrificial spacers serve as intermediary structures that facilitate cavity formation. These temporary structures enable the creation of complex air gap geometries using conventional fabrication processes, then are removed to leave the final desired structure, thus managing manufacturing complexity.
Data Source
AI summary
A semiconductor structure and a fabrication method are provided. The semiconductor structure includes: a base substrate; gate structures and source/drain plugs over the base substrate; source/drain contact structures on the source/drain plugs; gate contact structures on the gate structures; and a dielectric layer on the gate structures and the source/drain plugs. Cavities are formed between the gate structures and the source/drain plugs along a surface of the base substrate. The dielectric layer encloses tops of the cavities.