FINFET Contact Etch Stop Structure for Uniform Contact Depth
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Solution Overview
Problem
Contact depth variation in FINFET devices due to topography on the wafer leads to uneven contact features, which can cause circuit defects such as tilting, voids, and increased aspect ratios, making it difficult to fill contact holes completely.
Innovation Solution
A method involving the formation of a contact etch stop layer (CESL) with a controlled thickness profile and subsequent inter-layer dielectric (ILD) layer recessing to ensure uniform contact feature depth across the wafer, reducing the aspect ratio of trenches and preventing voids.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If contact features are formed on top of fins and isolation structures with topography variation, then circuit functionality is achieved, but contact depth variation occurs leading to tilting and circuit defects
Solution Approach 1:
The method performs preliminary planarization by forming an interlayer dielectric layer and performing chemical mechanical polishing (CMP) before contact hole formation. This preliminary action flattens the topography including fins and isolation structures, creating a uniform surface that eliminates contact depth variation and prevents tilting of contact features, thereby resolving the contradiction between circuit reliability and manufacturing precision
Solution Approach 2:
The patent introduces an interlayer dielectric layer as an intermediary between the topography (fins and isolation structures) and the contact features. This intermediary layer absorbs the topography variations and provides a uniform base for contact hole formation, preventing the transmission of depth variations to the final contact features while maintaining circuit functionality
2Reliability
If contact holes are made deep and narrow to reach underlying structures, then electrical connection is achieved, but voids form under contact features making detection difficult
Solution Approach 1:
The method performs preliminary planarization through CMP processing before forming contact holes. This creates a flat surface that allows contact holes to be formed with uniform depth and geometry, preventing the formation of deep and narrow holes that would be difficult to fill completely. The uniform geometry also makes void detection easier, resolving the contradiction between electrical connection reliability and void detection difficulty
Solution Approach 2:
The patent changes the geometric parameters of contact holes by first planarizing the surface, which transforms the contact hole geometry from deep and narrow to more uniform and accessible. This parameter change enables complete filling of contact holes and facilitates void detection, while still achieving the required electrical connection
3Length of stationary object
If contact features are formed with high aspect ratio trenches, then deep electrical connection is achieved, but filling becomes difficult and voids increase
Solution Approach 1:
The patent performs preliminary planarization by forming an interlayer dielectric layer and executing CMP processing before contact hole formation. This reduces the aspect ratio of trenches by creating a flat surface, making the trenches shallower and wider. This preliminary action enables easier and more complete filling of contact features while maintaining the required contact depth for electrical connection
Data Source
AI summary
An integrated circuit includes a substrate, an isolation feature disposed over the substrate, a fin extending from the substrate above the isolation feature, and a gate structure disposed directly over the isolation feature. The integrated circuit further includes a first dielectric layer disposed directly above the isolation feature and adjacent to the gate structure, and a first etch stop layer disposed between the first dielectric layer and the isolation feature. The integrated circuit further includes a second dielectric layer disposed directly above the first dielectric layer, and a second etch stop layer disposed between the first and the second dielectric layers and between the gate structure and the second dielectric layer. The first etch stop layer is also disposed between the gate structure and the second etch stop layer. A conductive feature is directly above the isolation feature and directly contacting the first dielectric layer.