FinFET Contact and S/D Depth Variation Across Mixed Gate Pitches
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor manufacturing processes struggle to efficiently fabricate multi-gate transistors with different constructions to meet varying design needs, such as high speed and low leakage, while maintaining similar process windows and reducing costs.
Innovation Solution
The integration of FinFET devices with different constructions, such as CMOS configurations, allows for the fabrication of transistors with varying designs on a single IC chip, utilizing FinFETs with distinct materials and gate structures to address specific design requirements, while maintaining compatibility with existing fabrication processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multi-gate transistors with different constructions are fabricated to meet varying design needs (high speed, low leakage), then design requirements are satisfied, but manufacturing complexity and process diversity increase
Solution Approach 1:
The patent applies local quality by implementing different FinFET constructions in different regions of the semiconductor device. First FinFETs have a first construction optimized for certain design needs (e.g., high speed), while second FinFETs have a second construction optimized for other needs (e.g., low leakage). This allows each region to have the specific transistor characteristics required for its function, thereby meeting varying design requirements without requiring the entire device to use a single complex construction type.
2Reliability
If different FinFET constructions are used to meet specific design requirements, then performance is optimized, but fabrication process complexity increases
Solution Approach 1:
The patent segments the fabrication process into distinct stages: forming mandrels with first and second patterns, selectively forming spacers based on the mandrel patterns, and forming gate structures accordingly. This segmentation allows different FinFET constructions to be created through a systematic, step-by-step approach rather than requiring a single complex fabrication process, thereby optimizing performance while managing manufacturing complexity.
Solution Approach 2:
The patent employs preliminary action by first forming mandrels with different patterns before creating the final FinFET structures. The spacers are formed based on these pre-established mandrel patterns, which then guide the subsequent gate structure formation. This preliminary structuring simplifies the overall fabrication process by breaking down complex tasks into manageable preliminary steps that can be systematically executed.
3Reliability
If FinFETs with distinct materials and gate structures are integrated, then design-specific performance is achieved, but manufacturing cost increases
Solution Approach 1:
The patent applies universality by using a common fabrication process framework that can produce multiple types of FinFETs with different constructions. The same basic process steps (mandrel formation, spacer formation, gate structure formation) are used to create both first and second FinFETs, just with different material selections and pattern configurations. This multi-functional approach allows a single fabrication line to produce design-specific transistors without requiring separate dedicated processes for each type, thereby achieving design-specific performance while controlling manufacturing cost.
Data Source
AI summary
A semiconductor device includes a first transistor and a second transistor. The first transistor includes a first gate structure of a first gate pitch, a first channel region, and a first source/drain (S/D) feature contacting the first channel region and having a first S/D depth. The second transistor includes a second gate structure of a second gate pitch, a second channel region, and a second S/D feature contacting the second channel region and having a second S/D depth. The semiconductor device also includes a first contact plug overlapping the first S/D feature and having a first width, and a second contact plug overlapping the second S/D feature and having a second width. The first gate pitch is different from the second gate pitch. The first S/D depth is different from the second S/D depth. The second width is larger than the first width.