FinFET Contact Structure With Dielectric ESL for Shorting Margin
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Solution Overview
Problem
As semiconductor devices shrink, the separation distance between metal gate contacts and source/drain contacts decreases, making it challenging to maintain sufficient separation and prevent shorting during fabrication, especially due to overlay errors in lithography processes.
Innovation Solution
A method is introduced that involves forming a dielectric etch-stop layer (ESL) between the source/drain contacts and gate spacers, which enlarges the separation distance and provides a greater margin for error by being selectively deposited on dielectric components, thereby reducing the risk of shorting and improving the accuracy of lithography patterning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes are reduced to increase functional density, then productivity and cost efficiency are improved, but the separation distance between metal gate contact and source/drain contact decreases, increasing the risk of shorting
Solution Approach 1:
The method forms the dielectric etch-stop layer between the metal gate contact and source/drain contact before final lithography patterning. This preliminary action establishes a physical barrier that pre-defines the separation distance, ensuring sufficient isolation is maintained even when subsequent lithography overlay errors occur during scaling to smaller feature sizes.
Solution Approach 2:
The dielectric etch-stop layer acts as an intermediary structure between the metal gate contact and source/drain contact. This intermediate layer provides an additional isolation barrier that mediates the separation requirement, allowing the contacts to be positioned closer together while maintaining reliable electrical isolation through the dielectric material.
2Productivity
If feature sizes are reduced to increase functional density, then manufacturing cost is reduced, but lithography overlay errors become more significant, making it difficult to maintain sufficient separation distance
Solution Approach 1:
The dielectric etch-stop layer is formed before final lithography patterning to pre-establish the separation geometry. This preliminary structural definition reduces dependence on lithography overlay precision, as the physical separation is determined by the etch-stop layer thickness and position rather than solely by lithographic pattern alignment.
Solution Approach 2:
The method changes the controlling parameter for separation distance from lithography pattern dimensions to dielectric layer thickness. By using deposition and etching processes to define the etch-stop layer thickness, the separation distance becomes controlled by a more precise and less variable parameter compared to lithographic patterning at scaled dimensions.
3Reliability
If separation distance is increased to prevent shorting, then reliability is improved, but device area increases, reducing functional density
Solution Approach 1:
The dielectric etch-stop layer provides localized quality enhancement at the critical interface between metal gate contact and source/drain contact. Rather than uniformly increasing separation distance across the entire device, the method concentrates the isolation function in a specific local region where the etch-stop layer is positioned, maintaining reliable shorting prevention while minimizing overall device area expansion.
Data Source
AI summary
A method includes providing a semiconductor structure having a metal gate structure (MG), gate spacers disposed on sidewalls of the MG, and a source/drain (S/D) feature disposed adjacent to the gate spacers; forming a first metal layer over the S/D feature and between the gate spacers; recessing the first metal layer to form a trench; forming a dielectric layer on sidewalls of the trench; forming a second metal layer over the first metal layer in the trench, wherein sidewalls of the second metal layer are defined by the dielectric layer; and forming a contact feature over the MG to contact the MG.