FINFET Contact Etch Stack for Uniform Contact Depths
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Solution Overview
Problem
Contact depth variation and void formation during FINFET device fabrication due to uneven topography, leading to circuit defects and reliability issues.
Innovation Solution
A method involving the formation of contact etch stop layers (CESL) and inter-layer dielectric layers to achieve uniform contact depths across the wafer, reducing the aspect ratio of trenches and ensuring consistent contact feature formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If contact features are formed on top of fins and isolation structures with uneven topography, then contact features can be formed across the wafer, but contact depth variation occurs and contact features may tilt over time
Solution Approach 1:
The patent applies preliminary action by forming an inter-layer dielectric layer and performing a recess process before contact hole etching. This recess step pre-compensates for the topography variation caused by taller fins, ensuring that the contact holes will have uniform depths when etched subsequently, thereby preventing contact feature tilting over time
Solution Approach 2:
The patent applies local quality by selectively removing the inter-layer dielectric layer only in regions where fins are located, while leaving it intact in isolation structure regions. This creates locally adapted contact hole depths that compensate for the underlying topography variations, ensuring uniform contact depths across different wafer regions
2Manufacturing precision
If contact holes are made deep and narrow to reach the substrate, then contact features can be formed, but voids may form under the contact features
Solution Approach 1:
The patent applies preliminary action by pre-forming the inter-layer dielectric layer and performing the recess process before contact hole etching. This creates optimized contact hole geometries with reduced aspect ratios, allowing contact features to be formed without voids while maintaining precise depth control
Solution Approach 2:
The patent applies parameter changes by modifying the contact hole geometry through the recess process, which changes the depth and cross-sectional area parameters. This optimization reduces the aspect ratio of contact holes, enabling complete filling with contact material and preventing void formation
3Adaptability or versatility
If contact features are formed with varying depths, then contact features can accommodate the topography, but circuit defects may occur over time due to tilting
Solution Approach 1:
The patent applies preliminary action by performing the recess process on the inter-layer dielectric layer before contact hole etching. This pre-compensation step ensures that contact holes will have uniform depths, preventing contact feature tilting and maintaining circuit stability over time while still accommodating the underlying topography
Data Source
AI summary
An integrated circuit includes a substrate, an isolation feature disposed over the substrate, a fin extending from the substrate above the isolation feature, and a gate structure disposed directly over the isolation feature. The integrated circuit further includes a first dielectric layer disposed directly above the isolation feature and adjacent to the gate structure, and a first etch stop layer disposed between the first dielectric layer and the isolation feature. The integrated circuit further includes a second dielectric layer disposed directly above the first dielectric layer, and a second etch stop layer disposed between the first and the second dielectric layers and between the gate structure and the second dielectric layer. The first etch stop layer is also disposed between the gate structure and the second etch stop layer. A conductive feature is directly above the isolation feature and directly contacting the first dielectric layer.