FinFET Contact Etch Stop Structure for Over-Etch Prevention
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In the manufacturing of integrated circuits, there is a challenge in preventing over-etching during the formation of source/drain vias and contacts, which can lead to leakage current and reduced device performance due to the limitations of existing etch stop layers and dielectric materials.
Innovation Solution
The use of an additional plasma treatment to form an oxidation region in dielectric materials and a middle contact etch stop layer with different etch selectivity, combined with a self-aligned-contact process, to prevent over-etching and ensure precise formation of source/drain vias and contacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing etch stop layers and dielectric materials are used during source/drain via and contact formation, then the manufacturing process is simpler, but over-etching occurs leading to leakage current and reduced device performance
Solution Approach 1:
The patent divides the etch stop function into multiple distinct layers: a first etch stop layer (silicon nitride) positioned deeper in the structure, and a second etch stop layer (oxidized silicon nitride) positioned closer to the source/drain regions. This segmentation allows each layer to serve specific protective functions, preventing over-etching while maintaining manufacturing feasibility through systematic process steps.
Solution Approach 2:
The patent applies plasma treatment to form an oxidation region in the dielectric material before etching source/drain vias and contacts. This preliminary oxidation creates a modified dielectric region with different etch characteristics, establishing a protective barrier in advance that prevents over-etching during subsequent processing steps.
2Manufacturing precision
If plasma treatment and additional etch stop layers are implemented, then over-etching is prevented and device performance improves, but the manufacturing process becomes more complex
Solution Approach 1:
The plasma treatment to form the oxidation region is performed as a preliminary step before via etching. This advance preparation creates a protective oxidized dielectric region that self-regulates the etching process, ensuring precise via formation without requiring complex real-time control mechanisms.
Solution Approach 2:
The oxidized dielectric region acts as an intermediary layer between the etch process and the underlying structures. This intermediate oxidized region modifies the etch characteristics, providing a controlled interface that prevents direct over-etching of sensitive underlying layers while maintaining a relatively simple overall process flow.
3Ease of manufacture
If conventional dielectric materials are used without plasma treatment, then the manufacturing process is simpler, but leakage current increases due to over-etching
Solution Approach 1:
The patent changes the physical and chemical parameters of the dielectric material by applying plasma treatment to create an oxidation region. This parameter change (oxidation state) fundamentally alters the etch characteristics of the dielectric, transforming it from a vulnerable material prone to over-etching into a protective barrier that prevents leakage current while adding only one process step.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the risk of leakage current and improves the accuracy and reliability of via formation, enhancing the electrical performance and manufacturing efficiency of integrated circuits.
Implementation Method 1
an additional plasma treatment to form an oxidation region in dielectric materials
Data Source
AI summary
A semiconductor structure includes a semiconductive fin, a gate structure, a plurality of source/drain regions, an un-oxidized dielectric cap, and an oxidized dielectric cap. The gate structure extends across the semiconductive fin. The source/drain regions are over the semiconductive fin and at opposite sides of the gate structure. The un-oxidized dielectric cap is atop the gate structure. The oxidized dielectric cap is atop the oxidized dielectric cap.