FinFET Contact Formation via Etch Stop Layer Modification
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Solution Overview
Problem
The increasing demand for high-functional and high-integration semiconductor devices requires advanced manufacturing methods to achieve fine patterns and three-dimensional structures, such as FinFETs, while maintaining reliability and integration levels.
Innovation Solution
A method involving the formation of active fins, source/drain regions, and etch stop layers, with specific impurity ion implantation and etching processes to create corrugated surfaces and enhance contact areas, utilizing wet and dry etching techniques with appropriate gases to achieve precise pattern formation and integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional planar MOSFET structures are used, then manufacturing is simpler, but device characteristics are limited and integration density is low
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional FinFET structures with vertical fins extending from the substrate. This dimensional change increases the effective channel area and integration density while maintaining manufacturability through established etching and deposition processes adapted for vertical geometries
2Productivity
If fine patterns with small widths are implemented, then integration density increases, but manufacturing precision requirements increase and reliability may deteriorate
Solution Approach 1:
The patent employs multiple ion implantation steps with varying energy levels and angles to precisely control dopant distribution in fine patterns. Etch stop layers are strategically positioned at specific depths to enable selective removal and maintain pattern fidelity during fabrication, allowing high integration density with controlled precision
3Area of stationary object
If etch stop layer is completely removed to form contacts, then contact area is maximized, but source/drain region damage increases
Solution Approach 1:
The patent performs preliminary ion implantation into the etch stop layer before contact formation to modify its etch characteristics. This preliminary action enables selective removal of the etch stop layer at contact locations while preserving the source/drain regions, achieving both adequate contact area and source/drain integrity through pre-conditioned selective etching
4Ease of manufacture
If standard etching processes are used, then process simplicity is maintained, but etching loss increases and pattern fidelity decreases
Solution Approach 1:
The patent introduces etch stop layers as intermediary elements between the interlayer dielectric and source/drain regions. These layers enable selective etching with high fidelity by providing distinct etch rate differences, reducing lateral etching loss and improving pattern transfer accuracy while maintaining process simplicity through sequential etching steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method improves the degree of integration and reliability of semiconductor devices by maintaining a wide contact area between source/drain regions and contact plugs, reducing etching loss, and enhancing the etch rate of etch stop layers, thus supporting high-performance semiconductor device manufacturing.
Implementation Method 1
forming an impurity region within the interlayer dielectric layer by implanting a first impurity ion through the first opening
Implementation Method 2
The forming of the second opening may be performed by a wet etching process
Implementation Method 3
The removal of the etch stop layer may be performed by a dry etching process
Implementation Method 4
The anisotropic dry etching process, a gas including Cl2, CHF3, CF4, or combinations thereof may be used as an etching gas
Implementation Method 5
In the isotropic dry etching process, a gas including NH3 or NF3 gas may be used as an etching gas
Data Source
AI summary
A method of manufacturing a semiconductor device includes forming active fins on a substrate; forming source/drain regions on the active fins on both sides of a gate structure, the gate structure extending in a direction intersecting with a direction in which the active fins extend; forming an etch stop layer on the source/drain regions; forming an interlayer dielectric layer on the etch stop layer; forming a first opening by partially removing the interlayer dielectric layer so as not to expose the etch stop layer; forming an impurity region within the interlayer dielectric layer by implanting a first impurity ion through the first opening; forming a second opening by removing the impurity region so as to expose the etch stop layer; implanting a second impurity ion into the exposed etch stop layer; and removing the exposed etch stop layer.