FinFET Source/Drain Contact Inverted T-Shape Parasitic Capacitance
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Solution Overview
Problem
In semiconductor fabrication, the close proximity of merged source/drain contacts to adjacent gates creates parasitic capacitance, leading to increased power consumption and reduced circuit speed due to limited space for transistor placement in CMOS technology below 14 nm nodes.
Innovation Solution
A method is developed to form a merged source/drain contact in an inverted 'T' shape, which reduces parasitic capacitance by creating recesses in the contact area not covered by a reverse contact mask and filling these recesses with dielectric material, thereby minimizing the overlap with gate spacers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If merged source/drain contact is placed close to adjacent gates to minimize transistor distance, then transistor density is improved, but parasitic capacitance increases
Solution Approach 1:
The patent extracts the harmful overlapping region between the source/drain contact and gate spacer by creating a recess in the contact structure. This removes the parasitic capacitance-generating area while preserving the electrical connection function, effectively separating the harmful electrical interaction from the necessary physical proximity.
Solution Approach 2:
The source/drain contact is segmented into two distinct regions: a lower portion that maintains electrical connection with the source/drain region, and an upper portion with a recess that reduces overlap with the gate spacer. This segmentation allows each region to fulfill its specific function while minimizing parasitic effects.
2Productivity
If thin spacer insulating material is used to separate contact and gate, then transistor placement density is improved, but parasitic capacitance increases
Solution Approach 1:
Instead of relying solely on the thin horizontal spacer to separate the contact from the gate, the patent introduces a vertical dimension by creating a recess in the contact structure. This dimensional change reduces the overlapping volume between conductive regions, thereby reducing parasitic capacitance while maintaining the same horizontal layout density.
3Reliability
If source/drain contact fully covers source/drain region, then electrical connection is improved, but parasitic capacitance with gate spacer increases
Solution Approach 1:
The contact structure is given different geometries in different regions: the lower portion maintains full coverage for reliable electrical connection, while the upper portion features a recessed area that reduces parasitic capacitance. This local differentiation allows each region to optimize for its specific function.
Data Source
AI summary
Various methods and structures for fabricating a contact for a semiconductor FET or FinFET device. A semiconductor FET structure includes a substrate, a source/drain region layer and source/drain contact. First and second gate spacers are adjacent respective first and second opposing sides of the source/drain contact. The source/drain contact is disposed directly on and contacting the entire source/drain region layer, and at a vertical level thereabove, the source/drain contact being recessed to a limited horizontal area continuing vertically upwards from the vertical level. The limited horizontal area horizontally extending along less than a full horizontal length of a vertical sidewall of the first and second gate spacers, and less than fully covering the source/drain region layer. A method uses a reverse contact mask to form a shape of the source/drain contact into an inverted âTâ shape.