FinFET Source/Drain Contact Over Dielectric Gate for Landing Margin
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Solution Overview
Problem
Advanced integrated circuits face challenges such as contact-to-gate bridging, narrow fin width for FinFETs leading to degraded contact landing margin, and increased contact resistance due to shrinking device sizes, which impact circuit performance and reliability.
Innovation Solution
A method for fabricating semiconductor structures with FinFETs that includes forming source/drain features using selective epitaxy and gate replacement with high-k metal gates, along with local interconnection features to enhance contact quality and reduce resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device size is scaled down for advanced technology nodes, then circuit density is improved, but contact landing margin is degraded
Solution Approach 1:
The contact structure transitions from a planar two-dimensional contact to a three-dimensional contact that extends vertically over the gate structure. This dimensional change allows the contact to maintain adequate landing area on the source/drain regions while spanning across the gate, effectively increasing the contact footprint without increasing the planar device footprint, thus maintaining circuit density while improving contact landing margin.
Solution Approach 2:
The contact is segmented into multiple portions: a first contact portion landing on the source/drain region, a second contact portion extending over the gate, and intermediate connecting portions. This segmentation allows each portion to fulfill specific functions - the first portion ensures electrical connection to the source/drain, while the second portion provides adequate landing margin and spans the gate, collectively resolving the contact landing margin issue.
2Productivity
If contact size is shrunk for high-density gate pitch requirement, then gate pitch density is improved, but contact resistance increases
Solution Approach 1:
The contact structure utilizes the vertical dimension to extend over the gate, effectively increasing the contact's electrical pathway length without increasing its planar footprint. This allows the contact to maintain low resistance by providing multiple parallel conduction paths through the intermediate portions while keeping the planar contact size small to achieve high gate pitch density.
Solution Approach 2:
The intermediate contact portions that extend over the gate act as mediators, providing continuous electrical connection between the source/drain contact and the overlying interconnect structures. These intermediate portions ensure adequate electrical pathways while spanning across the gate region, maintaining low contact resistance despite reduced planar contact dimensions.
3Reliability
If line end is reshaped by optical proximity correction to reduce line end shortening, then line end opening reliability is improved, but cell size increases or bridging occurs
Solution Approach 1:
Instead of modifying the line end shape in the planar dimension to prevent shortening, the invention extends the contact vertically over the gate region. This dimensional change provides adequate electrical connection and landing margin without requiring aggressive planar reshaping, thus avoiding increased cell size or bridging issues while maintaining line end opening reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Improves contact reliability and reduces resistance, enabling enhanced circuit performance and reliability by optimizing contact structures and interconnection design.
Implementation Method 1
forming source/drain features using selective epitaxy
Data Source
AI summary
The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a first active region and a second fin active region extruded from a semiconductor substrate; an isolation featured formed in the semiconductor substrate and being interposed between the first and second fin active regions; a dielectric gate disposed on the isolation feature; a first gate stack disposed on the first fin active region and a second gate stack disposed on the second fin active region; a first source/drain feature formed in the first fin active region and interposed between the first gate stack and the dielectric gate; a second source/drain feature formed in the second fin active region and interposed between the second gate stack and the dielectric gate; a contact feature formed in a first inter-level dielectric material layer and landing on the first and second source/drain features and extending over the dielectric gate.