FinFET Contact Mask Layout to Cut Parasitic Capacitance
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Solution Overview
Problem
As semiconductor devices continue to integrate more components into a given area with reduced minimum feature sizes, issues such as parasitic capacitance and performance degradation arise, particularly in applications like ring oscillators.
Innovation Solution
The use of a cut mask and a line mask combination to define contact regions in a dielectric layer, excluding dummy contacts through trim portions, reduces parasitic capacitance by minimizing unused areas where contacts are formed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the minimum feature size is reduced to increase integration density, then more components can be integrated into a given area, but parasitic capacitance increases and performance degrades
Solution Approach 1:
The patent applies segmentation by dividing the contact formation process into two distinct stages using two separate masks: a cut mask that defines the basic contact pattern and a line mask that adds trim portions to eliminate dummy contacts. This segmented approach allows precise control over contact regions, removing parasitic capacitance sources while maintaining the high integration density achieved through reduced minimum feature sizes.
Solution Approach 2:
The patent implements local quality by applying different mask patterns to different regions of the substrate. The trim portions of the line mask are selectively positioned to remove dummy contacts only in regions where they would create parasitic capacitance, while preserving necessary contacts in active device regions. This localized modification optimizes performance without compromising the overall high-density integration.
2Ease of manufacture
If dummy contacts are formed in unused areas to maintain pattern continuity, then manufacturing is simplified, but parasitic capacitance increases and performance degrades
Solution Approach 1:
The patent applies the extraction principle by using the line mask to remove (take out) the harmful dummy contacts from unused areas after the initial contact pattern is established by the cut mask. The trim portions of the line mask selectively eliminate dummy contacts that would create parasitic capacitance, while preserving the simplified manufacturing approach of using a continuous cut mask pattern across the entire substrate.
3Object-affected harmful factors
If contact regions are minimized to reduce parasitic capacitance, then performance improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the contact definition into two independent mask steps, which distributes the manufacturing precision requirements across two separate, well-controlled processes. The cut mask establishes the primary contact pattern with standard precision, while the line mask with trim portions provides fine-tuned adjustment to eliminate dummy contacts. This segmentation makes the overall process more robust than attempting to define all contact regions in a single high-precision step.
Data Source
AI summary
An embodiment method includes: forming fins extending from a semiconductor substrate; depositing an inter-layer dielectric (ILD) layer on the fins; forming masking layers on the ILD layer; forming a cut mask on the masking layers, the cut mask including a first dielectric material, the cut mask having first openings exposing the masking layers, each of the first openings surrounded on all sides by the first dielectric material; forming a line mask on the cut mask and in the first openings, the line mask having slot openings, the slot openings exposing portions of the cut mask and portions of the masking layers, the slot openings being strips extending perpendicular to the fins; patterning the masking layers by etching the portions of the masking layers exposed by the first openings and the slot openings; and etching contact openings in the ILD layer using the patterned masking layers as an etching mask.