3D Contact Plug Structure for FinFET Source/Drain Resistance
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Solution Overview
Problem
The increasing demand for high-performance semiconductor devices with fine patterns and high integration levels poses challenges in achieving improved electrical characteristics, particularly due to the limitations of planar metal oxide semiconductor FETs, which necessitate the development of three-dimensional channel devices like FinFETs.
Innovation Solution
A semiconductor device design featuring a substrate with active regions, gate structures, source/drain regions, contact plugs, and contact insulating layers, where the contact plugs have lower ends closer to the substrate than the source/drain regions, and gate structures with varying distances between the gate electrode layers and contact plugs to optimize electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If contact plugs are positioned at the same level as source/drain regions, then manufacturing process is simpler, but contact area is reduced and contact resistance increases
Solution Approach 1:
The contact plug extends in the vertical dimension below the source/drain region level, transforming a two-dimensional contact arrangement into a three-dimensional structure. This vertical extension increases the contact area with the source/drain region without occupying additional lateral space, thereby reducing contact resistance while maintaining manufacturing feasibility through standardized deposition processes.
Solution Approach 2:
The contact plug is nested within the vertical space beneath the source/drain region, utilizing the depth dimension that would otherwise be empty space. This nesting approach allows the contact plug to be positioned lower than the source/drain region without interfering with other device components, maximizing contact area while avoiding conflicts with the gate structure and other surface-level elements.
2Area of stationary object
If gate electrode layer is positioned closer to contact plugs, then device footprint is reduced, but electrical interference and parasitic capacitance increase
Solution Approach 1:
An insulating layer is introduced as an intermediary between the gate electrode layer and the contact plug. This intermediate insulating layer physically separates the conductive elements, preventing direct electrical contact and reducing parasitic capacitance. The insulating layer acts as a mediator that allows the gate and contact plug to be positioned in close proximity spatially while maintaining electrical isolation, thus reducing device footprint without increasing harmful electrical interference.
3Reliability
If source/drain regions are recessed deeper, then contact area with contact plugs increases, but manufacturing precision requirements increase
Solution Approach 1:
The contact plug is formed to extend below the source/drain region level before final device assembly, preparing the contact structure in advance. This preliminary positioning of the contact plug creates a pre-formed contact area that will interface with the source/drain region, allowing for controlled depth placement using standard deposition techniques rather than requiring precise post-formation recessing of the source/drain regions themselves.
Data Source
AI summary
A semiconductor device includes a substrate including an active region that extends in a first direction; a gate structure that intersects the active region and that extends in a second direction; a source/drain region on the active region on at least one side of the gate structure; a contact plug on the source/drain region on the at least one side of the gate structure; and a contact insulating layer on sidewalls of the contact plug, wherein a lower end of the contact plug is closer to the substrate than a lower end of the source/drain region.