FinFET Contact Plug Formation with Etch Stop Layer
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Solution Overview
Problem
The increasing demand for high integration in semiconductor devices makes it challenging to form contact plugs in restricted spaces, leading to parasitic capacitance and current delays due to excessive recessing of lower patterns during the formation process.
Innovation Solution
A semiconductor device design featuring active fins, isolation layers, a gate structure, source/drain regions, and contact plugs with an etch stop layer to minimize parasitic capacitance, where the contact plugs pass through the etch stop layer to connect with the source/drain regions, and the etch stop layer prevents excessive recessing of the interlayer insulating layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If contact plugs are formed in restricted spaces to achieve high integration, then device integration density is improved, but parasitic capacitance increases and current delays occur
Solution Approach 1:
The patent transitions from planar contact plug formation to three-dimensional FinFET architecture with vertically extending fins. Contact plugs are formed to contact the fin structures at multiple levels, utilizing vertical space to increase integration density while maintaining electrical performance by reducing parasitic capacitance through optimized contact geometry and positioning.
2Manufacturing precision
If lower patterns are excessively recessed during contact plug formation, then contact plug alignment is improved, but parasitic capacitance between gate electrode and contact plugs increases
Solution Approach 1:
The patent introduces an etch stop layer as an intermediary element between the interlayer insulating layer and the underlying structures. This etch stop layer precisely controls the recess depth of the interlayer insulating layer, preventing excessive recession that would cause the contact plug to contact the gate electrode and generate parasitic capacitance, while ensuring proper alignment of the contact plug with the source/drain regions.
3Object-generated harmful factors
If etch stop layer prevents excessive recessing, then parasitic capacitance is reduced, but manufacturing process complexity increases
Solution Approach 1:
The etch stop layer is formed in advance before the interlayer insulating layer is deposited and recessed. This preliminary action establishes a predetermined depth limit for the recess process, automatically preventing excessive recession that would create parasitic capacitance. The etch stop layer serves as a built-in depth control mechanism that simplifies process monitoring and ensures consistent electrical performance across manufacturing batches.
Data Source
AI summary
A semiconductor device including a fin field effect transistor (fin-FET) includes active fins disposed on a substrate, isolation layers on both sides of the active fins, a gate structure formed to cross the active fins and the isolation layers, source/drain regions on the active fins on sidewalls of the gate structure, a first interlayer insulating layer on the isolation layers in contact with portions of the sidewalls of the gate structure and portions of surfaces of the source/drain regions, an etch stop layer configured to overlap the first interlayer insulating layer, the sidewalls of the gate structure, and the source/drain regions, and contact plugs formed to pass through the etch stop layer to contact the source/drain regions. The source/drain regions have main growth portions in contact with upper surfaces of the active fins.