FinFET Contact Plug Etching to Protect Epitaxial Layers
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Solution Overview
Problem
In current FinFET fabrication, the formation of contact holes often results in the loss of epitaxial layers, which affects the operation of the device and necessitates an improvement in the fabrication process.
Innovation Solution
A method involving multistage etching processes is employed to form contact plugs, where a first etching process removes the ILD layer, and a second etching process removes the CESL to form a first contact hole, with the contact plug width varying adjacent to and under the CESL.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a photo-etching process is conducted to remove part of the ILD layer for forming contact holes, then contact holes can be formed, but epitaxial layers are lost thereby affecting device operation
Solution Approach 1:
The etching process is divided into two distinct stages: a first etching process that removes the ILD layer to form contact holes, and a second etching process that removes the CESL layer. This segmentation allows each etching step to be optimized independently, preventing excessive etching that would damage the epitaxial layer while still achieving complete contact hole formation.
Solution Approach 2:
A contact etch stop layer (CESL) is introduced as an intermediary layer between the ILD layer and the epitaxial layer. This CESL layer serves as a protective barrier during the first etching process, allowing the etch to proceed through the ILD layer while stopping before reaching the epitaxial layer, thereby preventing epitaxial layer loss.
2Loss of substance
If the contact plug width is reduced adjacent to the CESL, then epitaxial layer damage is reduced, but the contact plug structure becomes more complex
Solution Approach 1:
The contact plug is designed with non-uniform width, being narrower adjacent to the CESL layer and wider underneath it. This local variation in geometry allows the contact plug to minimize lateral etching damage to the epitaxial layer at the critical interface region, while maintaining sufficient contact area in the lower region for effective electrical connection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces damage and consumption of epitaxial layers, thereby improving the performance and reliability of the semiconductor device.
Implementation Method 1
performing a first etching process to remove the ILD layer
Implementation Method 2
performing a second etching process to remove the CESL for forming a first contact hole
Data Source
AI summary
A method for fabricating a semiconductor device includes the steps of forming a metal gate on a substrate, a contact etch stop layer (CESL) adjacent to the metal gate, and an interlayer dielectric (ILD) layer around the gate structure, performing a first etching process to remove the ILD layer, performing a second etching process to remove the CESL for forming a first contact hole, and then forming a first contact plug in the first contact hole. Preferably, a width of the first contact plug adjacent to the CESL is less than a width of the first contact plug under the CESL.