FinFET Contact Plug Gapfill With Selective Bottom-Up Deposition
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor industry faces challenges in forming contact plugs for FinFET devices, particularly in reducing contact plug resistance, avoiding peeling and corrosion during chemical mechanical polishing (CMP), and enhancing gapfill capability, as feature sizes decrease and integration density increases.
Innovation Solution
The solution involves forming low-resistance contact plugs by non-conformally and selectively depositing barrier layers, eliminating barrier layers where possible, and using a bottom-up deposition process to form alloy or non-alloy interfaces between conductive plugs and vias, while also employing surface treatments to alter the properties of dielectric layers and improve adhesion and deposition rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional contact plug formation methods are used, then manufacturing process is simpler, but contact plug resistance is high and gapfill capability is poor
Solution Approach 1:
The contact plug formation process is segmented into multiple distinct steps: surface treatment of the dielectric layer, selective barrier layer deposition in specific regions, and bottom-up conductive material filling. This segmentation allows each step to be optimized independently, achieving low resistance and good gapfill capability while maintaining manufacturability through modular process design.
Solution Approach 2:
Surface treatment is performed as a preliminary action before barrier layer deposition and conductive material filling. This preliminary surface modification prepares the dielectric layer by altering its properties to enable better adhesion and control subsequent deposition processes, thereby reducing contact plug resistance and improving overall formation quality.
Solution Approach 3:
Barrier layers are selectively deposited in specific regions rather than uniformly across the entire contact area. This local quality approach places barrier layers only where needed to prevent peeling and corrosion during CMP, while leaving other regions open for optimal conductive material filling, thus achieving low resistance without excessive process complexity.
2Reliability
If barrier layers are deposited to prevent peeling and corrosion, then reliability improves, but deposition complexity and process steps increase
Solution Approach 1:
Barrier layers are selectively deposited only in specific regions where peeling and corrosion protection is needed, rather than applying a uniform barrier layer across all contact areas. This localized approach maintains reliability by protecting vulnerable regions while minimizing overall process complexity and material usage.
Solution Approach 2:
Surface treatment is performed as a preliminary action before barrier layer deposition, modifying the dielectric layer properties to enhance subsequent barrier layer adhesion and effectiveness. This preliminary preparation ensures reliable protection against peeling and corrosion during CMP while maintaining a streamlined overall process.
3Manufacturing precision
If surface treatments are applied to alter dielectric layer properties, then adhesion and deposition rates improve, but process steps and complexity increase
Solution Approach 1:
Surface treatment is performed as a preliminary action before subsequent deposition steps, modifying the dielectric layer properties to enable better adhesion and control deposition rates. This single preliminary step consolidates multiple potential process interventions into one efficient operation, improving manufacturing precision without proportionally increasing overall process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces contact plug resistance, prevents peeling and corrosion, and enhances gapfill capability, leading to more reliable and efficient contact plug formation in FinFET devices.
Implementation Method 1
non-conformally depositing a conductive material in the opening, the conductive material filling the opening in a bottom-up manner
Implementation Method 2
performing a surface treatment process on sidewalls of the opening, the surface treatment process reducing a deposition rate of the conductive material on the sidewalls of the opening
Data Source
AI summary
A semiconductor device and a method of forming the same are provided. A method includes forming a gate over a semiconductor structure. An epitaxial source/drain region is formed adjacent the gate. A dielectric layer is formed over the epitaxial source/drain region. An opening extending through the dielectric layer and exposing the epitaxial source/drain region is formed. A conductive material is non-conformally deposited in the opening. The conductive material fills the opening in a bottom-up manner.