FinFET Contact Plug Isolation Layout for Open Circuit Prevention
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Solution Overview
Problem
In semiconductor manufacturing, particularly for FinFETs, there is a challenge in ensuring that contact plugs extend to the source/drain features without causing open circuits, while also minimizing parasitic capacitance between the gate stack and the contact plug.
Innovation Solution
The configuration of CMD features with specific dimensions (W1, W2, W3) and distances (S1, S2, S3) between them is used to isolate contact plugs, ensuring they extend to the source/drain features and minimizing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If CMD features are added to isolate contact plugs, then open circuit risk is reduced, but parasitic capacitance increases
Solution Approach 1:
The patent optimizes the parameters of CMD features, specifically their dimensions and spacing distances, to balance open circuit prevention with parasitic capacitance reduction. The distance between CMD features and source/drain features is set to a specific range (greater than a threshold value) to provide adequate isolation while minimizing the capacitive effect. The size and shape of CMD features are also controlled to achieve optimal isolation effectiveness with minimal parasitic capacitance.
Solution Approach 2:
The patent applies partial action by selectively placing CMD features only where necessary to prevent open circuits, rather than uniformly isolating all contact plugs. The spacing distance is set to exceed the minimum threshold only in areas where open circuit risk is highest, while using smaller distances in areas where the risk is lower. This partial application of isolation reduces overall parasitic capacitance while maintaining adequate protection against open circuits.
2Reliability
If spacing between CMD features is increased, then open circuit risk is reduced, but device area increases
Solution Approach 1:
The patent implements local quality by varying the spacing distance between CMD features and source/drain features based on local requirements. The spacing is set to be greater than a threshold value only in areas where open circuit risk is high, while maintaining smaller spacing in areas where the risk is low. This localized adjustment of spacing optimizes open circuit prevention without unnecessarily increasing the overall device area.
Solution Approach 2:
The patent uses partial action by applying increased spacing distances only where necessary to prevent open circuits, rather than uniformly increasing spacing across the entire device. This selective application of larger spacing distances achieves adequate open circuit prevention while minimizing the increase in device area.
Data Source
AI summary
A method includes forming a fin structure over a substrate, forming a first source/drain feature and a second source/drain feature over the fin structure, forming a dielectric material over the first source/drain feature and the second source/drain feature, patterning the dielectric layer into insulating features, and forming a first contact plug on the first source/drain feature and a second contact plug on the second source/drain feature. The insulating features include a first insulating feature and a second insulating feature on opposite sides of the first source/drain feature, and a third insulating feature and a fourth insulating feature on opposite sides of the second source/drain feature. The first insulating feature is longer than the third insulating feature. The distance between the first and second insulating features is greater than the distance between the third and fourth insulating features.