FinFET Contact Plug Formation Using Sacrificial Layer

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Solution Overview

Problem

Conventional FinFET fabrication faces issues such as 'tiger tooth' due to poor accuracy in forming contact holes, affecting the interconnection of contact plugs and overall device performance.

Innovation Solution

A method involving the formation of a sacrificial layer on the gate structure and interlayer dielectric layer, followed by creating a first contact plug and removing the sacrificial layer, then forming a conformal dielectric layer around the contact plug and gate structure to improve precision and accuracy in contact hole formation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If contact holes are formed using conventional methods, then the fabrication process is simple, but the accuracy and precision of contact hole formation deteriorates leading to tiger tooth issues

Engineering Contradiction:
Improvecontact hole formation accuracyVSAvoidfabrication process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

A sacrificial layer is formed on the gate structure before contact hole formation. This preliminary structure enables precise contact hole formation by providing a defined etch stop and alignment reference, thereby improving manufacturing precision without significantly increasing overall process complexity

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The sacrificial layer acts as an intermediary element between the gate structure and the contact plug. It facilitates accurate contact hole formation by serving as a temporary structure that guides the etching process, then is removed after serving its purpose

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If contact holes are formed with poor accuracy, then the fabrication process is faster, but the interconnection of contact plugs and overall device performance deteriorates

Engineering Contradiction:
Improveinterconnection reliabilityVSAvoidfabrication time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The sacrificial layer is formed in advance to establish precise alignment and depth control for contact holes. This preliminary structure ensures reliable interconnection by preventing misalignment and varying depths, while the subsequent removal of the sacrificial layer minimizes time loss

Inventive Principle:
Principle #10Preliminary action

3Manufacturing precision

If a sacrificial layer is formed and later removed, then the precision of contact plug formation is improved, but the fabrication process complexity increases

Engineering Contradiction:
Improvecontact plug formation precisionVSAvoidfabrication process steps
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The sacrificial layer is formed as a preliminary structure that enables precise contact plug formation. It provides a defined etch stop and alignment reference, improving precision by ensuring consistent contact hole depth and position

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The sacrificial layer is temporarily introduced to enable precise contact plug formation, then removed after serving its alignment and depth control function. This approach maintains precision while minimizing the impact on overall process complexity

Inventive Principle:
Principle #34Discarding and recovering

Data Source

PatentUS9728455B2Semiconductor device and method for fabricating the same
Publication Date: 2017.08.08 UNITED MICROELECTRONICS CORP
  • US9728455B2 patent drawing
  • US9728455B2 patent drawing
  • US9728455B2 patent drawing

AI summary

A method for fabricating semiconductor device includes the steps of: providing a substrate having a gate structure thereon and an interlayer dielectric (ILD) layer surrounding the gate structure; forming a sacrificial layer on the gate structure; forming a first contact plug in the sacrificial layer and the ILD layer; removing the sacrificial layer; and forming a first dielectric layer on the gate structure and the first contact plug.