Fin-FET Contact Plug Shaping for Voltage Uniformity
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Solution Overview
Problem
Conventional Fin-FET structures face issues with uneven voltage distribution due to their three-dimensional structure, affecting their quality and performance, and existing semiconductor structures fail to meet the requirements of miniaturization, high integration, high performance, and low power consumption.
Innovation Solution
A semiconductor structure with fin and gate structures on a substrate, featuring a dielectric layer and contact plugs with trapezoid or pentagon shapes, formed using patterned mask layers to improve fabrication yields and electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional Fin-FET structure with 90-degree corners is used, then fabrication process is simple, but voltage distribution becomes uneven affecting device quality
Solution Approach 1:
The patent applies asymmetry by modifying the conventional 90-degree corner fin structure to include rounded corners with a specific radius of curvature. This asymmetric modification to the corner geometry creates more uniform electric field distribution and voltage profiles across the channel, directly resolving the voltage distribution uniformity issue while maintaining fabrication compatibility
2Productivity
If miniaturization is pursued to meet high integration requirements, then device density increases, but conventional planar transistors no longer meet performance requirements
Solution Approach 1:
The patent transitions from planar transistors to three-dimensional Fin-FET structures, utilizing the vertical dimension to increase effective channel width and drive current. This dimensional change enables higher integration density while maintaining or improving transistor performance through the enhanced current drive capability provided by the fin structure
3Ease of manufacture
If contact plugs with conventional shapes are used, then fabrication process is straightforward, but fabrication yields cannot be upgraded
Solution Approach 1:
The patent introduces preliminary patterning actions by forming multiple mask layers with specific patterns before final contact plug formation. The first patterned mask layer defines initial contact regions, and the second patterned mask layer further refines the pattern, enabling precise contact plug placement that improves fabrication yields while maintaining process feasibility
Data Source
AI summary
A method of forming a semiconductor structure is provided. A substrate having a memory region is provided. A plurality of fin structures are provided and each fin structure stretching along a first direction. A plurality of gate structures are formed, and each gate structure stretches along a second direction. Next, a dielectric layer is formed on the gate structures. A first patterned mask layer is formed, wherein the first patterned mask layer has a plurality of first trenches stretching along the second direction. A second patterned mask layer on the first patterned mask layer, wherein the second patterned mask layer comprises a plurality of first patterns stretching along the first direction. Subsequently, the dielectric layer is patterned by using the first patterned mask layer and the second patterned mask layer as a mask to form a plurality of contact vias. The contact holes are filled with a conductive layer.