FinFET Source/Drain Contact Recess Depth for Resistance Balance
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Solution Overview
Problem
As transistor sizes shrink, manufacturing processes become increasingly complex to reduce resistance while maintaining device performance, particularly in source/drain contact plugs of FinFETs, where existing methods fail to achieve a balance between channel and contact resistance.
Innovation Solution
The method involves forming n-type and p-type source/drain contact recesses with varying depths, with the n-type recess being deeper than the p-type recess, to optimize the balance between channel and contact resistance, using epitaxy layers and etching processes to create conductive plugs with specific depths and doping concentrations, and forming silicide regions to reduce contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If transistor size is reduced to increase integration density, then device miniaturization is achieved, but manufacturing complexity increases
Solution Approach 1:
The patent segments the source/drain regions into n-type and p-type categories with different processing requirements. By dividing the manufacturing approach into material-specific processes, the patent manages the complexity of advanced node fabrication while achieving miniaturization, allowing each segment to be optimized independently
Solution Approach 2:
The patent performs preliminary classification and separation of n-type and p-type source/drain regions before the contact hole formation process. This preliminary action enables subsequent selective etching and simplifies the overall manufacturing flow at advanced nodes by pre-organizing the structure for differentiated processing
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the overall resistance of p-type FinFETs by reducing contact resistance while maintaining low resistance in n-type FinFETs, enhancing the performance of both types of transistors by adjusting the depth and doping of source/drain regions and conductive plugs.
Implementation Method 1
using epitaxy layers and etching processes to create conductive plugs with specific depths and doping concentrations
Implementation Method 2
performing a first etch through the first protection layer and having a first depth in the n-type source/drain region
Implementation Method 3
forming silicide regions to reduce contact resistance
Data Source
AI summary
A method includes forming an n-type Fin-Field Effect Transistor (FinFET) and a p-type FinFET. The forming of the n-type FinFFT includes: forming a first auxiliary gate stack over a first semiconductor fin; forming an n-type source/drain region on the first semiconductor fin; forming a patterned interlayer dielectric (ILD) layer over the n-type source drain; depositing a first protection layer over the patterned ILD layer and the n-type source/drain region; and performing a first etch through the first protection layer. The forming of the p-type FinFET includes: forming a second auxiliary gate stack over a second semiconductor fin; forming a p-type source/drain region on the second semiconductor fin; forming the patterned ILD layer over the p-type source drain region; depositing a second protection layer over the p-type source/drain region; and performing a second etch though the second protection layer.