FinFET Source/Drain Contact Layout for Lower Contact Resistance
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Solution Overview
Problem
As semiconductor devices continue to reduce minimum feature sizes for increased integration density, challenges arise in forming efficient source/drain contacts with reduced resistance and improved contact area, which affect the performance and efficiency of electronic components.
Innovation Solution
The formation of source/drain contacts in FinFET devices involves depositing conductive material over open regions and patterning it to create larger metal grains, reducing resistance by enhancing the contact area and grain size, thereby improving contact resistance and device efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional contact formation methods are used, then manufacturing process is simple, but contact resistance is high and contact area is limited
Solution Approach 1:
The method performs preliminary actions by depositing metal material over the entire surface including gate structures and isolation regions before patterning. This preliminary deposition creates a uniform metal layer that can be subsequently patterned to form contacts with optimized grain structure and reduced contact resistance, addressing the contradiction between simple process and low contact resistance.
Solution Approach 2:
The invention changes physical parameters by controlling metal grain size through the deposition and patterning process. By depositing metal over open regions and then patterning it, the method creates larger metal grains in the contact regions, which reduces contact resistance. This parameter change (grain size) directly addresses the technical contradiction.
2Productivity
If minimum feature sizes are reduced for increased integration density, then more components can be integrated, but contact formation becomes more difficult and resistance increases
Solution Approach 1:
The method transitions from forming contacts only at the top surface to depositing metal in multiple dimensions - over the gate structure, isolation regions, and open regions. This dimensional approach allows the contact metal to extend laterally and form optimized grain structures, making contact formation easier despite reduced feature sizes and increased integration density.
Solution Approach 2:
The contact formation process is segmented into distinct steps: depositing metal over the entire surface, then patterning it to define contact regions. This segmentation allows independent optimization of metal deposition parameters and contact patterning, facilitating easier manufacture at smaller feature sizes while maintaining low contact resistance.
3Reliability
If contact area is increased to reduce resistance, then contact resistance decreases, but device area increases
Solution Approach 1:
The method applies local quality by creating different metal grain sizes in different regions. The contact regions have larger metal grains due to the deposition over open regions followed by patterning, while other areas maintain their original structure. This localized optimization reduces contact resistance without requiring uniform area increase across the entire device.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method results in source/drain contacts with reduced resistance, potentially lowering contact resistance by 80-98% and enhancing device performance and efficiency.
Implementation Method 1
depositing a metal material over the isolation region, the gate structure, the source/drain structure, and the fin
Implementation Method 2
etching openings in the metal material, wherein each opening exposes the isolation region, wherein the metal material remains on a top surface of the source/drain region
Implementation Method 3
depositing an insulating material, wherein the insulating material fills the openings
Data Source
AI summary
A method includes forming an isolation region around a semiconductor fin; forming a gate structure over the semiconductor fin; forming a source/drain region in the semiconductor fin adjacent the gate structure; depositing a metal material covering the isolation region, the gate structure, the semiconductor fin, and the source/drain region; etching openings in the metal material, wherein each opening exposes the isolation region, wherein the metal material remains on a top surface of the source/drain region remains after etching the openings; and depositing an insulating material, wherein the insulating material fills the openings.