FinFET Contact Formation via Segmented Etching
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Solution Overview
Problem
In FinFET semiconductor devices, the self-aligned contact formation process leads to thinning of gate insulating layers, increasing the likelihood of shorts between contact members and gate electrodes, resulting in leakage and reduced device quality.
Innovation Solution
A non-self-aligned process is used to form the upper half of the contact hole, with a sidewall dielectric layer formed on the sidewalls, which is then used as a self-aligned mask to etch the lower half, reducing leakage and gate capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a self-aligned process is used to form contact holes, then manufacturing precision is improved, but the gate insulating layer thickness is reduced leading to increased shorting probability
Solution Approach 1:
The contact hole formation process is segmented into two distinct steps: first forming an upper portion of the contact hole through the interlayer dielectric, then forming a lower portion extending to the active region. This segmentation allows different etching conditions to be applied to each portion, preventing gate insulator thinning while maintaining alignment precision.
Solution Approach 2:
The upper portion of the contact hole is formed in advance before the lower portion. This preliminary action allows the gate area to be prepared and protected beforehand, preventing subsequent damage during the formation of the lower contact hole portion that would otherwise threaten gate-insulator integrity.
2Ease of manufacture
If the gate insulating layer is thinned during contact formation, then contact hole formation becomes easier, but leakage between gate and contact increases
Solution Approach 1:
The contact hole etching is divided into two segmented processes with different etching conditions. The first process forms the upper portion with conditions optimized for ease of formation, while the second process forms the lower portion with conditions that prevent gate insulator damage, thus eliminating leakage without sacrificing manufacturability.
Solution Approach 2:
The etching parameters (such as etch selectivity, depth, and conditions) are changed between the two contact hole formation steps. The first step uses parameters favorable for forming the upper contact hole, while the second step adjusts parameters to safely reach the active region without damaging the gate insulator, thereby preventing leakage.
3Device complexity
If conventional contact formation is used, then process simplicity is maintained, but gate capacitance increases
Solution Approach 1:
The contact hole formation is segmented into upper and lower portions with different etching conditions. This segmentation creates a more precise contact structure that reduces unnecessary capacitance between the gate and contact regions, lowering gate capacitance despite the increased process steps.
Solution Approach 2:
By changing etching parameters between the two contact hole formation steps, the contact structure achieves better geometric control and reduced overlap with the gate region. This parameter optimization reduces parasitic gate capacitance while the additional process steps maintain overall device performance.
Data Source
AI summary
A method of manufacturing a semiconductor device includes providing a substrate structure, which includes a substrate, one or more semiconductor fins on the substrate, a gate structure on each fin, an active region located in said fins, and an interlayer dielectric layer covering at the active region. The method includes forming a hard mask layer over the interlayer dielectric layer and the gate structure, and using an etch process with a patterned etch mask, forming a first contact hole extending through the hard mask layer and extending into a portion of the interlayer dielectric layer, using patterned a mask. The method further includes forming a sidewall dielectric layer on sidewalls of the first contact hole, and using an etch process with the sidewall dielectric layer as an etch mask, etching the interlayer dielectric layer at bottom of the first contact hole to form a second contact hole extending to the active region.