FinFET Contact Sheath Structure for Etching Precision
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Solution Overview
Problem
The high aspect ratio of fin-type field effect transistors (FinFETs) poses challenges in forming reliable contact openings and metal connectors, leading to issues with etching precision and reliability due to the tight spacing and high aspect ratio, which affects the device's performance and yield.
Innovation Solution
The formation of a conformal adhesion layer and subsequent sheath structures within the contact openings provides better isolation and tolerance during etching, allowing for the creation of smaller feature sizes and improved connectivity of metal connectors to the source and drain regions without direct contact with the gate electrode, enhancing the etching process window and device reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the gate width and channel length are shrunk to increase wafer area efficiency, then the device density and operation speed are improved, but the aspect ratio of the fins increases making etching and contact formation more difficult
Solution Approach 1:
The patent introduces a sheath structure as an intermediary layer between the metal connector and the high aspect ratio fin structure. This sheath structure, formed by depositing material conformally on the sidewalls of the contact opening, provides a tapered profile that facilitates etching and metal deposition processes, thereby resolving the manufacturing precision issues caused by high aspect ratios while maintaining the benefits of shrunk gate dimensions
2Speed
If the fin aspect ratio is increased to improve device performance, then the operation speed and area efficiency are enhanced, but the reliability of contact openings and metal connectors deteriorates
Solution Approach 1:
The patent changes the geometric parameters of the contact opening by forming a tapered profile through conformal deposition of the sheath structure. This parameter change transforms the vertical sidewall profile into a tapered profile, which improves the reliability of contact openings and metal connectors by reducing stress concentrations and facilitating more reliable etching and filling processes, while preserving the high aspect ratio fin structure needed for operation speed
3Area of stationary object
If the critical dimensions are reduced to increase device density, then the wafer area utilization is improved, but the process window for etching and contact formation narrows
Solution Approach 1:
The patent addresses the narrowed process window by introducing an additional dimensional element - the sheath structure with tapered profile. This dimensional addition provides extra process margin and flexibility, allowing the etching and metal deposition processes to accommodate variations more effectively, thereby widening the process window while maintaining reduced critical dimensions for high device density
Data Source
AI summary
A fin-type field effect transistor device including a substrate, a gate stack structure, spacers and source and drain regions is described. The spacers includes first and second spacers and a first height of the first spacer is larger than a second height of the second spacer. A dielectric layer disposed on the gate stack structure includes a contact opening exposing the source and drain regions, the first and second spacers and a portion of the gate stack structure. A sheath structure is disposed within the contact opening and the sheath structure is in contact with the first and second spacers and the exposed portion of the gate stack structure without covering the source and drain regions. A metal connector is disposed within the sheath structure and connected to the source and drain regions.