FinFET Gate Contact Placement Between Fins to Prevent Voids
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Solution Overview
Problem
As semiconductor devices undergo miniaturization, the formation of voids in metal gate stacks during the manufacturing of FinFETs leads to increased contact resistance due to constrained spacing between gate contacts and fins, which affects the integration density and performance of electronic components.
Innovation Solution
Constraining the spacing between gate contacts and metal gate stacks to avoid void formation, and cutting the metal gate stacks to prevent deformation, allowing for increased contact area and reduced contact resistance by forming gate contacts on portions of the stacks free from voids.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the spacing between gate contacts and fins is reduced to increase integration density, then more components can be integrated into a given area, but voids form in the metal gate stacks leading to increased contact resistance
Solution Approach 1:
The patent applies preliminary action by constraining the spacing between gate contacts and metal gate stacks before void formation can occur. By pre-establishing minimum spacing rules during the design and manufacturing process, the invention prevents void formation in advance, thereby maintaining low contact resistance while still achieving high integration density through optimized layout arrangements.
Solution Approach 2:
The patent changes the spacing parameter between gate contacts and metal gate stacks to optimal values that prevent void formation. By carefully controlling and adjusting this dimensional parameter, the invention achieves a balance where integration density is maximized without compromising contact resistance, as the constrained spacing ensures proper material deposition and prevents void formation during manufacturing.
2Ease of manufacture
If the metal gate stacks are not cut, then the manufacturing process is simpler, but deformation occurs leading to void formation and increased contact resistance
Solution Approach 1:
The patent applies segmentation by cutting the metal gate stacks into separate sections. This division prevents deformation that would otherwise occur in continuous, longer gate stack structures. By segmenting the gate stacks at appropriate locations, the invention maintains manufacturing precision and prevents void formation while adding a relatively simple cutting step to the manufacturing process.
3Ease of manufacture
If gate contacts are formed on portions with voids, then contact formation is simpler, but contact resistance increases affecting device performance
Solution Approach 1:
The patent applies local quality by ensuring that gate contacts are formed only on specific portions of the metal gate stacks that are free from voids. By identifying and targeting void-free regions for contact formation, the invention maintains low contact resistance while still achieving relatively simple contact formation processes. The local quality of the contact region is optimized independently from other areas of the device.
Data Source
AI summary
In an embodiment, a method includes: forming a first fin extending from a substrate; forming a second fin extending from the substrate, the second fin being spaced apart from the first fin by a first distance; forming a metal gate stack over the first fin and the second fin; depositing a first inter-layer dielectric over the metal gate stack; and forming a gate contact extending through the first inter-layer dielectric to physically contact the metal gate stack, the gate contact being laterally disposed between the first fin and the second fin, the gate contact being spaced apart from the first fin by a second distance, where the second distance is less than a second predetermined threshold when the first distance is greater than or equal to a first predetermined threshold.