Integrated FinFET Source/Drain Contacts With Built-In Extensions
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Solution Overview
Problem
Current methods for forming device-level contacts in semiconductor devices, such as FinFETs, require separate processes for S/D contact extensions (MDX) that increase processing complexity, costs, and introduce additional barrier layers, leading to higher contact resistance and reduced device performance.
Innovation Solution
A method for forming semiconductor devices that integrates S/D contacts with built-in extension features, allowing for simultaneous deposition of conductive material to form S/D contacts and MDX, thereby reducing processing complexity and barrier layer interfaces, and enhancing device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If separate processes are used for forming S/D contacts and MDX, then S/D contacts can be formed with proper structure, but processing complexity increases and additional barrier layers are introduced
Solution Approach 1:
The patent combines the formation of source/drain contacts and mid-contact extensions into a single integrated process. Dummy contacts are formed simultaneously with S/D contacts using the same patterning and deposition steps, eliminating the need for separate MDX formation processes. This merging approach reduces processing complexity while maintaining proper contact structure through the dummy contact design that guides subsequent etching and metallization steps.
2Manufacturing precision
If separate processes are used for forming S/D contacts and MDX, then S/D contacts can be formed with proper structure, but additional barrier layers are introduced leading to higher contact resistance
Solution Approach 1:
By forming S/D contacts and MDX in the same process window with identical barrier and conductive layer deposition, the patent eliminates additional barrier layer interfaces that would otherwise be created by separate processing steps. The merged approach ensures continuous barrier and conductive material layers across both contact regions, reducing contact resistance and improving electrical reliability.
3Productivity
If current methods are used for forming device-level contacts, then processing can be completed, but processing windows for subsequent fabrication steps are reduced
Solution Approach 1:
The patent performs preliminary formation of dummy contacts that extend beyond the final contact openings during the initial patterning and deposition steps. These dummy structures serve as pre-formed guides for subsequent self-aligned etching processes, enlarging the processing window for vias and interconnect formation by providing broader target areas that accommodate alignment variations in later fabrication steps.
Data Source
AI summary
A semiconductor structure includes a first epitaxial source/drain (S/D) feature disposed over a first semiconductor fin, a second epitaxial S/D feature disposed over a second semiconductor fin and adjacent to the first epitaxial S/D feature, an interlayer dielectric (ILD) layer disposed over the first and the second epitaxial S/D features, a dielectric feature disposed In the ILD layer and contacting the second epitaxial S/D feature, and a conductive feature disposed in the ILD layer and contacting the first epitaxial S/D feature, where a portion of the conductive feature extends to contact the dielectric feature.