FinFET Fin Structure Tuning for Core and I/O Critical Dimensions

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Solution Overview

Problem

Current semiconductor fabrication processes for FinFET devices cannot simultaneously satisfy the demand for greater critical dimension in core regions for increased channel volume and smaller critical dimension in input/output regions for improved short channel effect.

Innovation Solution

A method is developed to fabricate semiconductor devices by forming fin-shaped structures on a substrate with different critical dimensions for core and input/output regions, where a patterned mask is used to cover the input/output region, and an epitaxial growth process is applied to the core region to enlarge the fin-shaped structure, thereby increasing the channel width without altering the critical dimension of the input/output region.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If the critical dimension of fin-shaped structures is increased in core regions to increase channel volume, then the channel volume is improved, but the short channel effect control deteriorates

Engineering Contradiction:
Improvechannel volumeVSAvoidshort channel effect control
Core Design Contradiction:
Volume of moving objectVSReliability

Solution Approach 1:

The patent applies different critical dimensions to fin-shaped structures in different regions: larger critical dimension in core regions to increase channel volume, and smaller critical dimension in input/output regions to improve short channel effect control. This regional differentiation resolves the contradiction by optimizing each region for its specific functional requirements.

Inventive Principle:
Principle #3Local quality

2Reliability

If the critical dimension of fin-shaped structures is decreased in input/output regions to improve short channel effect, then the short channel effect control is improved, but the channel volume decreases

Engineering Contradiction:
Improveshort channel effect controlVSAvoidchannel volume
Core Design Contradiction:
ReliabilityVSVolume of moving object

Solution Approach 1:

The patent implements region-specific fin-shaped structure dimensions where input/output regions use smaller critical dimensions for superior short channel effect control, while core regions use larger critical dimensions for maximum channel volume. This local optimization strategy allows each region to achieve its primary performance target.

Inventive Principle:
Principle #3Local quality

3Ease of manufacture

If a single critical dimension is used for all fin-shaped structures, then the manufacturing process is simplified, but the device performance for different regions cannot be optimized

Engineering Contradiction:
Improvefabrication process simplicityVSAvoidregion-specific performance optimization
Core Design Contradiction:
Ease of manufactureVSAdaptability or versatility

Solution Approach 1:

The patent divides the substrate into distinct regions (core regions and input/output regions) with different fin-shaped structure critical dimensions. This segmentation enables independent optimization of each region's performance characteristics while maintaining a manageable fabrication process through selective processing steps.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach allows for increased channel width in core regions while maintaining the critical dimension of fin-shaped structures in input/output regions, effectively addressing the dual demands of channel volume and short channel effect, thereby enhancing the overall performance of the semiconductor device.

Implementation Method 1

an epitaxial growth process is applied to the core region to enlarge the fin-shaped structure

Methodology Applied
Scientific EffectEpitaxial growth: Epitaxy

Data Source

PatentUS20250169169A1Semiconductor device and method for fabricating the same
Publication Date: 2025.05.22 UNITED MICROELECTRONICS CORP
  • US20250169169A1 patent drawing
  • US20250169169A1 patent drawing
  • US20250169169A1 patent drawing

AI summary

A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; forming a patterned mask on the second region; and performing a process to enlarge the first fin-shaped structure so that the top surfaces of the first fin-shaped structure and the second fin-shaped structure are different.