FinFET Cut Isolation Revision for Overlay Compensation
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Solution Overview
Problem
Advanced FinFET manufacturing faces challenges in ensuring proper alignment during photolithography, leading to overlay shifts and misalignment issues due to inaccuracies in reticle overlay, particularly in complex active regions with varying feature sizes, which can result in unlanded trench silicide contacts and inconsistent etching.
Innovation Solution
A method is introduced to revise the size of fin cut isolation openings in integrated circuit layouts by determining the number of fins to be cut with same source/drain connection and the fin cut isolation pitch, allowing for adjustments in the width of these openings to compensate for overlay inaccuracies, thereby improving alignment and reducing misalignment issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If standard photolithography alignment is used, then manufacturing process is simple, but overlay accuracy deteriorates leading to misalignment
Solution Approach 1:
The patent applies preliminary action by revising the fin cut isolation opening dimensions in the layout design before photolithography fabrication. This pre-compensation adjusts the opening size based on predicted overlay shifts, so that when overlay inaccuracies occur during manufacturing, the trench silicide contacts still land correctly on the source/drain regions. The revision is calculated and applied in advance to counteract expected alignment deviations.
2Reliability
If fin cut isolation opening size is increased, then overlay shift margin is improved, but trench silicide contact alignment deteriorates
Solution Approach 1:
The patent applies parameter changes by precisely adjusting the fin cut isolation opening dimensions to specific revised values that simultaneously provide adequate overlay shift margin and ensure proper trench silicide contact alignment. The opening size is neither too large nor too small, but optimized to a specific parameter range that balances both requirements - large enough to accommodate overlay variations but small enough to maintain contact alignment precision.
3Manufacturing precision
If overlay compensation is applied, then alignment accuracy is improved, but process steps are increased
Solution Approach 1:
The patent implements overlay compensation through preliminary action by incorporating dimension revisions directly into the layout design stage. This approach integrates compensation into the existing design and fabrication workflow without adding separate process steps. The revised fin cut isolation opening dimensions are applied in advance during layout preparation, allowing standard photolithography processes to produce accurately aligned features without requiring additional manufacturing operations.
Data Source
AI summary
A method to address overlay accuracy compensation using finFET cut isolation revisions is disclosed. For an integrated circuit (IC) layout including at least a portion of an active region including a plurality of gates extending over a plurality of fins, prior to optical proximity correction of the IC layout: the method determines a number of fins to be cut with same source/drain connection by a fin cut isolation opening, and determines a fin cut isolation pitch in the gate length direction of the plurality of gates. The method revises a size of a fin cut isolation opening in the IC layout based on a number of fins to be cut with same source/drain connection by the fin cut isolation opening and the fin cut isolation pitch in the gate length direction. The revision in size of the fin cut isolation compensates for overlay inaccuracy.