FinFET Fin Formation Using Cut Mask Patterning
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Solution Overview
Problem
Conventional FinFET fabrication techniques face challenges in achieving uniform fin thickness and pitch, especially at small process technologies like 32 nm or smaller, which is critical for transistor performance and density.
Innovation Solution
A method involving the formation of a whole-field arrangement of conductive fins with uniform pitch and thickness on a semiconductor wafer, followed by selective removal using a cut mask to define features for transistor devices, ensuring consistent fin and gate line structures across the wafer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional FinFET fabrication techniques are used to decrease transistor size and increase transistor density, then transistor density is improved, but fin thickness uniformity and fin pitch uniformity deteriorate
Solution Approach 1:
The patent segments the fin formation process into two distinct stages: first forming a continuous conductive layer across the entire wafer, then selectively removing portions to create individual fins. This segmentation allows the continuous layer to establish uniform dimensions before patterning, resolving the contradiction between high transistor density and fin uniformity.
Solution Approach 2:
The patent performs preliminary formation of a continuous conductive layer with uniform thickness across the entire wafer before selective removal. This preliminary action ensures that all fins are derived from a uniformly thick layer, guaranteeing fin thickness uniformity even when densely packed, thereby enabling high transistor density without sacrificing precision.
2Quantity of substance
If conventional FinFET fabrication techniques are used to decrease transistor size and increase transistor density, then transistor density is improved, but fin pitch uniformity deteriorates
Solution Approach 1:
The patent segments the fin formation process into continuous layer formation followed by selective removal. The continuous layer is formed with uniform properties across the entire wafer, and subsequent patterning creates uniform fin pitch by removing material according to a precise pattern, enabling both high density and uniform pitch.
Solution Approach 2:
The patent changes the approach from directly patterning individual fins to first creating a continuous layer with controlled physical parameters (uniform thickness and composition), then using patterned removal to define fin positions. This parameter control in the continuous layer stage ensures uniform fin pitch regardless of transistor density.
3Ease of manufacture
If selective removal of conductive fins is performed to define transistor features, then transistor device features are defined, but fin dimension uniformity may deteriorate
Solution Approach 1:
The patent performs preliminary formation of a continuous conductive layer with precisely controlled uniform dimensions before selective removal. This preliminary establishment of uniform dimensions ensures that even after selective removal to define transistor features, the remaining fins maintain uniform thickness and pitch, preventing deterioration of fin dimension uniformity.
Data Source
AI summary
A fabrication process for a FinFET device is provided. The process begins by providing a semiconductor wafer having a layer of conductive material such as silicon. A whole-field arrangement of fins is then formed from the layer of conductive material. The whole-field arrangement of fins includes a plurality of conductive fins having a uniform pitch and a uniform fin thickness. Next, a cut mask is formed over the whole-field arrangement of fins. The cut mask selectively masks sections of the whole-field arrangement of fins with a layout that defines features for a plurality of FinFET devices. The cut mask is used to remove a portion of the whole-field arrangement of fins, the portion being unprotected by the cut mask. The resulting fin structures are used to complete the fabrication of the FinFET devices.