FinFET Gate Electrode Formation via Damascene Process
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Solution Overview
Problem
The fabrication of FinFET devices for memory chips is hindered by challenges in doping the tri-gate structure, particularly due to vertical angle implantation leading to depletion of the gate side portion, and other manufacturing issues that limit their implementation in memory devices.
Innovation Solution
A method involving the use of a damascene process to form FinFET and MOSFET gate electrodes of different materials over semiconductor substrates, with a mask layer and insulating layers to manage the doping and etching processes, allowing for the formation of FinFET and MOSFET devices in separate areas, and optionally stacking FinFET gates with insulating layers for increased integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If vertical angle implantation doping is used for FinFET gate, then doping efficiency is improved, but gate side portion depletion occurs
Solution Approach 1:
The patent divides the gate structure into distinct regions (first gate region in cell area, second gate region in peripheral circuit area) with different doping approaches. The mask layer is segmented to allow selective doping angles - vertical angle implantation for the first gate region where depletion is acceptable, and different doping for the second gate region where uniformity is critical.
Solution Approach 2:
Different doping strategies are applied to different parts of the gate structure. The first gate region uses vertical angle implantation optimized for doping efficiency, while the second gate region uses a different approach optimized for uniformity. The mask layer has different properties or configurations in different areas to enable this localized quality approach.
2Device complexity
If FinFET gate electrode is formed using conventional methods, then fabrication simplicity is maintained, but etching and doping difficulties arise
Solution Approach 1:
A mask layer is introduced as an intermediary element between the conventional fabrication process and the FinFET gate formation. This mask layer facilitates the etching and doping processes by providing selective protection and definition, making these difficult steps more manageable while maintaining overall process simplicity.
Solution Approach 2:
The mask layer is formed in advance before the gate electrode deposition. This preliminary action prepares the structure for subsequent etching and doping steps, allowing these operations to proceed more easily by pre-defining the regions that need to be processed differently.
3Reliability
If FinFET devices are implemented in memory chips, then device performance is improved, but manufacturing limitations prevent reliable fabrication
Solution Approach 1:
The patent applies different manufacturing approaches to different regions: the cell area uses FinFET structures with vertical angle implantation optimized for performance, while the peripheral circuit area uses a different configuration optimized for manufacturing reliability. This allows high-performance FinFETs to be implemented in memory cells while maintaining manufacturability through alternative approaches in peripheral circuits.
Data Source
AI summary
In one aspect, a semiconductor substrate is provided having a cell area and a peripheral circuit area, and a mask layer is formed over the cell area and the peripheral circuit area of the semiconductor substrate. A FinFET gate is fabricated by forming a first opening in the mask layer to expose a first gate region in the cell area of the semiconductor substrate, and then forming a FinFET gate electrode in the first opening using a damascene process. A MOSFET gate fabricated by forming a second opening in the mask layer to expose a second gate region in the peripheral circuit area of the semiconductor substrate, and then forming a MOSFET gate electrode in the second opening using a damascene process.