Fin-FET Gate Alignment via Damascene Trench Formation

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Solution Overview

Problem

Current fin field effect transistor (Fin-FET) fabrication methods face challenges in achieving well-aligned gate structures with reduced channel width, leading to issues like short channel effects, drain-induced barrier lowering, and sub-threshold slope, which affect device performance.

Innovation Solution

A method involving a damascene-like process to form a trench in an insulation layer, exposing an upper portion of the fin structure, followed by the formation of a gate structure within this trench, ensuring self-alignment and a narrower gate channel region, which is less than the source and drain regions, thereby reducing parasitic resistance and improving performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If a conventional gate structure is formed through direct patterning and etching, then the manufacturing process is simpler, but the gate structure cannot achieve well alignment with the gate channel region and cannot reduce the channel width effectively

Engineering Contradiction:
Improvealignment precision between gate structure and gate channel regionVSAvoidcomplexity of gate structure formation process
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The gate structure formation process is divided into multiple stages: first forming an insulation layer covering the fin structure, then creating a trench through selective removal, and finally forming the gate structure within the trench. This segmentation enables precise alignment and width control that cannot be achieved through direct patterning.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention transitions from two-dimensional planar patterning to three-dimensional trench-based gate structure formation. By utilizing the vertical dimension to create the trench and then forming the gate structure within it, the process achieves superior alignment precision and width control compared to conventional planar methods.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If the gate channel region width is reduced to improve short channel effect control, then the channel control is improved, but the alignment between gate structure and channel region becomes more difficult to achieve

Engineering Contradiction:
Improvecontrol over short channel effectsVSAvoidalignment precision between gate structure and channel region
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The gate structure automatically aligns with the gate channel region through the self-aligned nature of the trench formation process. The trench is formed by removing insulation material above the fin structure, which inherently positions the subsequent gate structure in correct alignment with the channel region, eliminating the need for separate alignment steps.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The insulation layer is formed and patterned in advance to define the trench location and dimensions before the gate structure is formed. This preliminary action establishes the precise geometry and alignment of the gate channel region, which then guides the gate structure formation process to achieve accurate positioning.

Inventive Principle:
Principle #10Preliminary action

3Manufacturing precision

If a damascene-like process is used to form the gate structure, then the gate structure achieves well alignment and fine edge quality, but the manufacturing process becomes more complex

Engineering Contradiction:
Improveedge quality and alignment of gate structureVSAvoidease of gate structure fabrication
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The insulation layer serves as an intermediary material that facilitates the formation of the gate structure with precise alignment and fine edge quality. By forming the trench through selective removal of this intermediary layer, the process achieves superior dimensional control and edge quality that would be difficult to obtain through direct etching of the gate structure.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS8871575B2Method of fabricating field effect transistor with fin structure
Publication Date: 2014.10.28 UNITED MICROELECTRONICS CORP
  • US8871575B2 patent drawing
  • US8871575B2 patent drawing
  • US8871575B2 patent drawing

AI summary

A method of fabricating a field effect transistor with a fin structure is described. At least a fin structure is formed on a substrate. A planar insulation layer covering the fin structure is formed. A trench is formed in the insulation layer and intersects the fin structure both lengthwise. The trench is disposed over portions of the fin structure, and a lengthwise direction of the trench intersects a lengthwise direction of the fin structure, and thereby an upper portion of the fin structure is exposed to the trench. The exposed upper portion of the fin structure will serve as a gate channel region. A gate structure covering the upper portion is formed within the trench. The upper portion of the fin structure may be further trimmed.