FinFET Decoupling Capacitor Integration via Fin Merging
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Solution Overview
Problem
The integration of decoupling capacitors with aggressively scaled semiconductor devices is challenging due to the need for large areas for efficient decoupling, which is problematic for miniaturized integrated circuits like FinFETs.
Innovation Solution
The integration of a decoupling capacitor with fin type field effect transistors (FinFETs) on the same substrate, where the decoupling fin structure acts as a first electrode, a node dielectric layer is used, and a metal contact to the source and drain regions serves as the second electrode, positioned underlying the power lines to semiconductor fin structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If decoupling capacitors are integrated with scaled semiconductor devices, then decoupling efficiency is improved, but area requirement increases which conflicts with miniaturization goals
Solution Approach 1:
The patent merges the decoupling capacitor structure with the existing finFET fabrication process by forming decoupling fins alongside semiconductor fins using the same mandrel and spacer structures. This integration allows decoupling functionality to be embedded within the device area rather than added separately, achieving efficient decoupling without proportionally increasing total device area.
Solution Approach 2:
The patent utilizes the vertical dimension by forming three-dimensional fin structures that extend upward from the substrate. The decoupling fins are formed vertically and connected through conductive plugs to upper metallization layers, effectively using vertical space to achieve capacitor functionality without proportionally increasing the horizontal footprint of the device.
2Stability of the object's composition
If larger decoupling capacitors are used to reduce power line fluctuation, then power supply stability is improved, but device size increases which is problematic for miniaturized ICs
Solution Approach 1:
The patent implements a nested structure where decoupling fins are formed within the same lateral footprint as the semiconductor fins, utilizing the same mandrel and spacer fabrication steps. The decoupling structure is essentially nested within the existing device geometry, allowing power supply stabilization functionality to be embedded without significantly increasing overall device volume.
Solution Approach 2:
The patent employs composite material structures combining semiconductor fins for active devices with decoupling fins for capacitor functionality, both formed from the same base semiconductor material but differentiated by doping and structural configuration. This composite approach allows dual functionality within a unified structure, achieving power stability without proportional volume increase.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for efficient decoupling of power lines, reducing fluctuations and enabling higher drive currents in transistors with smaller dimensions, while maintaining a compact form factor suitable for miniaturized semiconductor devices.
Implementation Method 1
a node dielectric layer and a second electrode provided by the metal contact to the source and drain regions
Data Source
AI summary
An electrical device including a plurality of fin structures. The plurality of fin structures including at least one decoupling fin and at least one semiconductor fin. The electrical device includes at least one semiconductor device including a channel region present in the at least one semiconductor fin, a gate structure present on the channel region of the at least one semiconductor fin, and source and drain regions present on source and drain region portion of the at least one semiconductor fin. The electrical device includes at least one decoupling capacitor including the decoupling fin structure as a first electrode of the decoupling capacitor, a node dielectric layer and a second electrode provided by the metal contact to the source and drain regions of the semiconductor fin structures. The decoupling capacitor is present underlying the power line to the semiconductor fin structures.