FinFET Decoupling Capacitor Mitigates Rail Voltage Droop
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Solution Overview
Problem
FinFETs exhibit larger gate capacitances compared to planar FETs, leading to rail voltage droop when gates switch, which decreases switching speed and affects the timing of semiconductor chips.
Innovation Solution
A decoupling capacitor is integrated into the finFET structure, utilizing a fin and gate configuration with a dielectric layer to minimize voltage droop by storing charge and maintaining rail voltages, formed on the same substrate as the finFETs with the fin and gate coupled to DC voltage rails and insulated from a conductor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If finFET structure is used to improve transistor performance, then transistor performance is improved, but gate capacitance increases causing rail voltage droop
Solution Approach 1:
The patent combines the decoupling capacitor with the finFET structure by integrating the fin and gate into a shared substrate configuration. The fin and gate of the decoupling capacitor are formed on the same substrate as the finFET, sharing common substrate real estate and creating a compact integrated structure that provides decoupling functionality without adding separate discrete components.
Solution Approach 2:
The fin and gate structures serve dual purposes: they form part of the active finFET circuitry while simultaneously functioning as decoupling capacitor elements. The same fin and gate that provide transistor switching capability also serve as capacitor plates for charge storage, enabling the structure to perform both switching and voltage stabilization functions.
2Power
If finFET structure is used to improve transistor performance, then transistor performance is improved, but switching speed decreases due to voltage droop
Solution Approach 1:
The decoupling capacitor is positioned and configured in advance near the finFET structure to preemptively counteract voltage droop before it significantly impacts switching performance. The capacitor is pre-charged during stable voltage periods and ready to immediately discharge and compensate when switching events cause voltage drops, maintaining optimal switching conditions.
Solution Approach 2:
The decoupling capacitor provides preliminary counter-action to the harmful voltage droop effect by storing charge in advance and releasing it when droop occurs. This preemptive charge storage and discharge mechanism opposes the voltage droop before it can significantly degrade switching speed, maintaining stable rail voltages during transitions.
3Reliability
If decoupling capacitor is added to mitigate voltage droop, then voltage stability is improved, but device complexity increases
Solution Approach 1:
The decoupling capacitor is merged with the finFET structure by using the same substrate and forming the capacitor fin and gate alongside the transistor fin and gate. This integration eliminates the need for separate discrete capacitor components and reduces the overall device complexity while maintaining voltage stability functionality.
Solution Approach 2:
The fin and gate structures perform multiple functions simultaneously: they provide transistor switching capability and serve as decoupling capacitor elements. This multi-functionality reduces the total number of components needed and simplifies the overall device architecture while delivering both switching performance and voltage stabilization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The decoupling capacitor effectively mitigates voltage droop caused by finFET switching, maintaining stable rail voltages and improving switching speed and overall chip timing by providing a local power source.
Implementation Method 1
a dielectric layer electrically insulating both the gate and the fin from the conductor
Implementation Method 2
The decoupling capacitor effectively mitigates voltage droop caused by finFET switching, maintaining stable rail voltages by providing a local power source
Data Source
AI summary
Embodiments herein describe a decoupling capacitor that may include multiple fin and gate structures electrically insulated from a conductor (e.g., a metal layer) by a thin dielectric. The fins and gates may be electrically coupled to a first voltage rail (e.g., VHIGH) while the conductor is coupled to a second voltage rail (e.g., VLOW). In this manner, the fins and gates in combination form a first “plate” which is electrically insulated from the conductor which forms a second “plate” of a capacitor. In one embodiment, the decoupling capacitor is formed on the same substrate as the finFETs, and thus, can be disposed proximate to the finFETs—e.g., on the same layer in the chip or side-by-side. In one example, at least a portion of the decoupling capacitor and the finFET may be formed using the same fabrication steps.