FinFET Decoupling Fins for High-Frequency Response

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Solution Overview

Problem

Off-chip capacitance in high-speed integrated circuit devices has a slow frequency response, making it unsuitable for decoupling capacitance, and on-chip decoupling capacitor design faces challenges in providing sufficient decoupling capacitance for high-frequency circuits.

Innovation Solution

The method involves forming fin-type field-effect transistors (finFETs) with decoupling fins of increased height and varying widths for NFET and PFET regions, using different strain levels and chemical compositions in layer portions A and B, and selectively etching to create n-type and p-type fins, resulting in improved current control and capacitance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If off-chip capacitance is used for decoupling, then device complexity is reduced, but frequency response becomes too slow for high-speed circuits

Engineering Contradiction:
Improvecapacitor arrangement complexityVSAvoidfrequency response
Core Design Contradiction:
Device complexityVSSpeed

Solution Approach 1:

The patent transitions from off-chip capacitor arrangements to on-chip decoupling capacitors by utilizing the vertical dimension of fin structures. The decoupling fins extend vertically from the substrate, creating three-dimensional capacitance structures that provide sufficient decoupling capacitance within the chip footprint while maintaining high-frequency response characteristics.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent integrates decoupling capacitor structures within the same chip substrate that hosts the finFET devices. The decoupling fins are formed in the same semiconductor layer as the device fins, nesting the capacitor functionality within the transistor structure itself, thereby reducing overall device complexity while maintaining performance.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Speed

If on-chip decoupling capacitors are implemented, then frequency response is improved, but sufficient decoupling capacitance is difficult to achieve

Engineering Contradiction:
Improvefrequency responseVSAvoiddecoupling capacitance
Core Design Contradiction:
SpeedVSQuantity of substance

Solution Approach 1:

The patent utilizes vertical fin structures extending from the substrate to increase the effective surface area for capacitance formation. By transitioning from planar to three-dimensional fin structures, the decoupling capacitance is significantly increased within the same chip area, providing sufficient capacitance for high-frequency operation.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent employs different chemical compositions in layer portion A and layer portion B of the semiconductor layer, with layer portion B having higher etch selectivity. This composite structure enables the formation of decoupling fins with optimized dimensions and capacitance characteristics through selective etching processes.

Inventive Principle:
Principle #40Composite materials

3Manufacturing precision

If selective etching is used to form A fins and B fins from precursor fins, then manufacturing precision is improved, but device complexity increases

Engineering Contradiction:
Improvefin formation precisionVSAvoidetching process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent applies different etch selectivities to different regions of the semiconductor layer by creating layer portion A and layer portion B with distinct chemical compositions. This local differentiation enables selective etching of B fins from A fins using the same etch chemistry, achieving high manufacturing precision without requiring multiple different etching processes.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the chemical composition parameter of the semiconductor layer to create regions with different etch rates. Layer portion B is formulated with higher etch selectivity compared to layer portion A, enabling precise control over fin formation through parameter-based differentiation rather than complex process sequencing.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10263014B2Fin-type field-effect transistor
Publication Date: 2019.04.16 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US10263014B2 patent drawing
  • US10263014B2 patent drawing
  • US10263014B2 patent drawing

AI summary

This invention relates to a fin field-effect transistor semiconductor structure. The method of forming the semiconductor structure can include patterning a plurality of precursor fins on a semiconductor layer having a layer portion A and a layer portion B. The semiconductor layer can be located on a substrate. The layer portion B can be selectively etched to form B fins and a top half of precursor fins. The layer portion A can be selectively etched to form A fins and the substrate can be etched to form a bottom half of the decoupling fins. The precursor fins can be removed to expose the A fins, the decoupling fins, and the B fins. One of the A fins and the B fins can form n-type fins and the other can form p-type fins.