FinFET Defect-Trapping Structure for High-Mobility Scaling

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Solution Overview

Problem

The scaling-down of MOS transistors in semiconductor devices to increase integration density leads to degradation in operational characteristics, necessitating research for techniques to enhance carrier mobility and improve electric characteristics.

Innovation Solution

A field-effect transistor design featuring a semiconductor substrate with a fin structure composed of a second semiconductor material having a different lattice constant, where the fin structure includes a lower portion elongated in one direction and upper portions protruding in a perpendicular direction, with a gate structure crossing the upper portions, and a method of fabricating this structure using epitaxial growth to form a defect-free upper portion.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If MOS transistors are scaled down to increase integration density, then integration density is improved, but operational characteristics degrade

Engineering Contradiction:

Improveintegration densityVSAvoidoperational characteristics

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The fin structure is segmented into a lower portion and multiple upper portions, with the lower portion serving as a defect-trapping base and the upper portions providing high-quality channel regions. This segmentation allows defects to be isolated in the lower portion while maintaining operational integrity in the upper portions.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different portions of the fin structure have different quality characteristics - the lower portion is designed to contain defects, while the upper portions are designed to be substantially defect-free. This local differentiation allows the device to function properly despite the presence of defects in certain regions.

Inventive Principle:

Principle #3Local quality

2Reliability

If the fin structure is made entirely of defect-free material, then operational characteristics improve, but manufacturing complexity increases

Engineering Contradiction:

Improveoperational characteristicsVSAvoidmanufacturing complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The invention converts the harmful effect of crystal defects into a beneficial design feature by intentionally creating a lower portion that traps defects. This approach, referred to as a 'defect trap' structure, allows defects to be confined to non-critical regions while maintaining high-quality channel regions for device operation.

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

3Ease of manufacture

If the fin structure uses a single material, then manufacturing is simpler, but carrier mobility is limited

Engineering Contradiction:

Improvematerial uniformityVSAvoidcarrier mobility

Core Design Contradiction:

Ease of manufactureVSSpeed

Solution Approach 1:

The fin structure employs composite materials - the lower portion uses a first semiconductor material while the upper portions use a second semiconductor material with different properties. This composite structure enables both defect management and enhanced carrier mobility in the channel regions formed by the second material.

Inventive Principle:

Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The design achieves reduced area and improved electric characteristics by confining crystal defects within the lower portion of the fin structure, allowing the upper portion to be formed of substantially defect-free semiconductor material, enhancing the performance of the field-effect transistor.

Implementation Method 1

forming an epitaxial layer in the lower trench and the upper trenches, wherein the epitaxial layer includes a semiconductor material having a lattice constant is different from that of the semiconductor substrate

Methodology Applied

Scientific EffectEpitaxial growth: Epitaxy

Data Source

PatentUS11843051B2Field effect transistor including multiple aspect trapping ratio structures

Publication Date: 2023.12.12 SAMSUNG ELECTRONICS CO LTD

AI summary

The present disclosure relates to a field-effect transistor and a method of fabricating the same. A field-effect transistor includes a semiconductor substrate including a first semiconductor material having a first lattice constant, and a fin structure on the semiconductor substrate. The fin structure includes a second semiconductor material having a second lattice constant that is different from the first lattice constant. The fin structure further includes a lower portion that is elongated in a first direction, a plurality of upper portions protruding from the lower portion and elongated in a second direction that is different from the first direction, and a gate structure crossing the plurality of upper portions.