FinFET Gate Dielectric Stack With Doped Interfacial Layer
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The device performance of fin-like field-effect transistors (FinFETs), particularly in terms of gate oxide capacitance (Cox) and Ion, is not satisfactory in advanced technology applications.
Innovation Solution
A method of forming a semiconductor device with a doped interfacial layer having a high k-value is introduced to enhance Cox and Ion, involving the formation of a doped interfacial layer with dopants such as Al, Hf, La, Sc, or Y, and a high-k dielectric layer over the channel region of the FinFET.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional gate oxide structure is used in FinFET, then the device structure is simple and easy to manufacture, but the gate oxide capacitance (Cox) and Ion are insufficient for advanced applications
Solution Approach 1:
The patent employs a composite gate dielectric structure consisting of multiple layers including a first gate dielectric layer, a second gate dielectric layer with higher k-value, and optionally a third gate dielectric layer. This composite structure combines materials with different electrical properties to achieve both high capacitance and manufacturability, resolving the contradiction between device performance and structural complexity.
Solution Approach 2:
The patent changes the physical and chemical parameters of the gate dielectric layers, specifically the k-value (dielectric constant) and thickness of each layer. By optimizing these parameters across multiple layers, the overall gate oxide capacitance is enhanced while maintaining a structured approach that facilitates manufacturing processes.
2Reliability
If the gate oxide capacitance is increased to improve Ion, then the device performance improves, but the manufacturing process becomes more complex
Solution Approach 1:
The gate dielectric is segmented into multiple distinct layers, each with specific thickness and k-value characteristics. This segmentation allows the total capacitance to be achieved through a distributed structure rather than a single complex layer, making the manufacturing process more manageable while still achieving the desired Ion performance.
Solution Approach 2:
By using composite gate dielectric materials with different k-values in separate layers, the patent achieves high overall capacitance without requiring any single layer to be excessively thin or complex, thereby maintaining ease of manufacture while improving Ion.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The doped interfacial layer increases the gate dielectric capacitance and Ion of the semiconductor device, thereby improving device performance.
Implementation Method 1
a doped interfacial layer (430) covering a portion of the fin structure, in which the doped interfacial layer (430) includes a dopant selected from the group consisting of Al, Hf, La, Sc, or Y
Data Source
AI summary
A device includes a channel layer, a gate structure, a first gate spacer, and a second gate spacer. The gate structure wraps around the channel layer. The first gate spacer and the second gate spacer are on opposite sides of the gate structure. The first gate spacer has a first portion and a second portion between the gate structure and the first portion of the first gate spacer, and a dopant concentration of the second portion of the first gate spacer is greater than a dopant concentration of the first portion of the first gate spacer.