FinFET Gate Dielectric Thickness Profiling for Etch Protection
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Solution Overview
Problem
As semiconductor devices undergo miniaturization, the reduction in minimum feature size leads to challenges such as fin damage and intrinsic leakage during etch processes, which affect the yield and reliability of FinFET devices.
Innovation Solution
A non-conformal gate dielectric layer is formed by alternating conformal and non-conformal sub-layers, resulting in a thicker layer over the top surface of the fin compared to the sidewalls, thereby protecting the fin from etch processes and improving device reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conformal gate dielectric layer is formed with uniform thickness, then the manufacturing process is simple and consistent, but the fin top surface is exposed during etch processes causing fin damage and intrinsic leakage
Solution Approach 1:
The gate dielectric layer is segmented into multiple sub-layers with different thicknesses: a first sub-layer with thickness T1 on the fin top surface and a second sub-layer with thickness T2 on the fin sidewalls, where T1 > T2. This segmentation allows the fin top surface to be adequately protected during etch processes while maintaining appropriate gate control, resolving the contradiction between fin protection and device simplicity.
Solution Approach 2:
Different regions of the fin structure receive different gate dielectric thicknesses tailored to their specific needs: the fin top surface receives a thicker dielectric layer (T1) for protection against etch damage and intrinsic leakage, while the fin sidewalls receive a thinner layer (T2) for optimal gate control. This local differentiation resolves the contradiction by providing enhanced protection where needed without unnecessarily complicating the overall structure.
2Reliability
If the gate dielectric layer is made thicker to protect the fin, then fin damage and intrinsic leakage are reduced, but the device dimensions increase affecting integration density
Solution Approach 1:
The gate dielectric layer implements local quality by providing different thicknesses at different locations: a thicker first sub-layer (T1) on the fin top surface for protection, and a thinner second sub-layer (T2) on the fin sidewalls. This ensures fin protection and intrinsic leakage reduction while minimizing the overall increase in device dimensions, thereby maintaining integration density.
Solution Approach 2:
The solution transitions from a single uniform thickness dimension to a multi-dimensional thickness distribution, where the gate dielectric layer thickness varies across different spatial dimensions (top surface vs. sidewalls). This dimensional differentiation allows protection where needed while controlling overall device footprint for high integration density.
3Reliability
If a non-conformal gate dielectric layer with varying thickness is formed, then fin protection is improved, but the manufacturing precision and process control become more difficult
Solution Approach 1:
The gate dielectric layer is formed as segmented sub-layers with distinct thicknesses (T1 on top surface, T2 on sidewalls) deposited in sequential steps. This segmentation approach allows for controlled deposition of each layer with specific thickness parameters, making the non-uniform thickness profile achievable through standardized deposition processes while maintaining manufacturing precision.
Solution Approach 2:
The thicker first sub-layer is deposited preliminary on the fin top surface before forming the thinner second sub-layer on the sidewalls. This preliminary action ensures that the critical fin top surface receives adequate protection thickness before the sidewall region is addressed, facilitating precise thickness control through a staged deposition process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the yield and reliability of FinFET devices by reducing fin damage and intrinsic leakage during post-gate etching processes.
Implementation Method 1
forming a conformal sublayer includes performing a first atomic layer deposition (ALD) process on the top surface and the sidewalls of the fin
Implementation Method 2
forming a non-conformal sublayer includes performing a physical vapor deposition (PVD) process on the conformal sublayer
Data Source
AI summary
A semiconductor device a method of forming the same are provided. The method includes forming a fin extending from a substrate and forming a gate dielectric layer along a top surface and sidewalls of the fin. A first thickness of the gate dielectric layer along the top surface of the fin is greater than a second thickness of the gate dielectric layer along the sidewalls of the fin.