FinFET Fin Height Control via Dielectric Etching
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Solution Overview
Problem
The challenge in semiconductor manufacturing is achieving consistent fin heights in 3D semiconductor devices like FinFETs, as existing methods struggle to control fin heights uniformly across a wafer, leading to performance inconsistencies.
Innovation Solution
A method involving the sequential formation of doped semiconductor layers on a substrate, patterning to form initial fins, covering them with a dielectric layer, and etching back to create an isolation layer that exposes the fins, allowing the fin height to be defined by the distance from the isolation layer's top surface, with the dielectric layer's thickness on the fins being less than on the substrate to improve etching accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If fins are formed directly on a substrate using conventional patterning methods, then the manufacturing process is simple, but the fin heights are inconsistent across the wafer
Solution Approach 1:
The manufacturing process is divided into distinct stages: forming initial fins through patterning, depositing a dielectric layer, and performing selective etching. This segmentation allows each step to be optimized independently, with the etching step specifically controlling fin height to achieve consistency across the wafer.
Solution Approach 2:
Initial fins are formed in advance as a preliminary structure before the final fin height is established. These initial fins serve as a base that is subsequently modified through controlled etching, allowing the final fin height to be precisely defined by the etching depth rather than the initial patterning.
2Manufacturing precision
If a thick dielectric layer is deposited on the initial fins, then complete coverage is achieved, but the etching depth becomes too large to control accurately
Solution Approach 1:
The dielectric layer is deposited with varying thickness across different regions: a first thickness on the initial fins and a second thickness on the substrate. This local quality differentiation ensures that the etching depth required to expose the first semiconductor layer is reduced, thereby improving etching accuracy and fin height control.
3Manufacturing precision
If the dielectric layer thickness on fins is reduced, then etching depth and improve accuracy, but complete coverage of the initial fin may be compromised
Solution Approach 1:
The dielectric layer is engineered with different thicknesses in different locations: sufficient thickness on the substrate for proper isolation and coverage, while maintaining a reduced thickness on the fins to enable precise etching control. This local differentiation resolves the contradiction between coverage and etching accuracy.
Data Source
AI summary
Provided are a semiconductor device and a method for manufacturing the same. An example method may include: forming a first semiconductor layer and a second semiconductor layer sequentially on a substrate, wherein the first semiconductor layer is doped; patterning the second and first semiconductor layers to form an initial fin; forming a dielectric layer on the substrate to substantially cover the initial fin, wherein a portion of the dielectric layer on top of the initial fin has a thickness sufficiently less than that of a portion of the dielectric layer on the substrate; etching the dielectric layer back to form an isolation layer, wherein the isolation layer partially exposes the first semiconductor layer, thereby defining a fin above the isolation layer; and forming a gate stack intersecting the fin on the isolation layer.