FinFET Dielectric Isolation Structure for Dense Transistor Layouts
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Solution Overview
Problem
The challenge in semiconductor manufacturing is achieving high integration density of electronic components while maintaining effective electrical isolation and miniaturization, particularly in the formation of transistor structures.
Innovation Solution
The implementation of a continuous poly on oxide definition edge (CPODE) structure in the front-end-of-line (FEOL) stage, which includes a dielectric stack penetrating fin structures to separate active regions, and the use of a replacement polysilicon gate (RPG) technique to form functional gate structures, enhancing electrical isolation and miniaturization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If continuous poly on oxide definition edge (CPODE) structure is implemented, then electrical isolation is improved, but device complexity increases
Solution Approach 1:
The CPODE structure divides the isolation region into distinct segments: a first portion extending between fins and a second portion extending over the gate structure. This segmentation allows each portion to serve specific isolation functions, improving electrical isolation while maintaining manageable structural complexity through modular design.
Solution Approach 2:
The continuous poly on oxide definition edge structure serves multiple functions simultaneously: it provides electrical isolation between adjacent transistors, defines the active region boundaries, and extends over the gate structure to maintain planarity. This multi-functionality reduces the need for separate isolation structures, thereby managing device complexity while improving electrical isolation.
2Length of moving object
If replacement polysilicon gate (RPG) technique is used, then miniaturization is improved, but manufacturing precision requirements increase
Solution Approach 1:
The RPG technique employs preliminary actions by first forming a dummy gate structure, then performing source/drain epitaxial growth, and finally replacing the dummy gate with the actual polysilicon gate. This sequence of preliminary actions enables precise control over transistor dimensions and facilitates miniaturization while managing fabrication precision requirements through staged processing.
Solution Approach 2:
The dummy gate structure serves as an intermediary element during the RPG process. It allows the epitaxial growth to proceed with precise dimensional control, and subsequently, it is replaced by the final polysilicon gate. This intermediary approach enables miniaturization by decoupling the dimensional definition step from the gate formation step, thereby managing manufacturing precision requirements.
3Reliability
If dielectric stack penetrates fin structures, then electrical isolation is improved, but manufacturing complexity increases
Solution Approach 1:
The CPODE structure merges the isolation function with the definition edge function by forming a continuous structure that penetrates the fin structures and extends over the gate. This merging eliminates the need for separate isolation trenches and cap structures, improving electrical isolation while simplifying the overall manufacturing process through consolidation of functions.
Solution Approach 2:
The dielectric stack is extended in the vertical dimension to penetrate through the fin structures and reach the substrate, providing three-dimensional electrical isolation. This dimensional extension improves isolation effectiveness without requiring additional lateral processing steps, thereby maintaining manufacturing ease while achieving superior electrical isolation.
Data Source
AI summary
The present disclosure provides a method of manufacturing a semiconductor structure. The method includes: providing a substrate; forming a fin structure on the substrate; forming a first dummy gate on the fin structure; forming a first trench through the first dummy gate; forming a dielectric stack, the dielectric stack including a first portion in the first trench, and a second portion over and connected to the first portion; depositing a cap layer over the second portion of the dielectric stack; patterning the cap layer and the dielectric stack to form a second trench separating the first portion from the second portion; and filling the second trench with a protective layer over the first portion of the dielectric stack.