FinFET Dielectric Recess Formation for Lower Parasitic Capacitance
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Solution Overview
Problem
The increase in parasitic capacitance between adjacent fins in Fin FETs degrades circuit speed and reduces device performance, posing a challenge in semiconductor manufacturing.
Innovation Solution
A method involving the formation of a crystalline shell around dielectric layers through annealing, followed by selective etching to create a concavity, which reduces metal gate capacitance and minimizes parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a standard planar dielectric layer is formed between adjacent fins, then the manufacturing process is simple, but parasitic capacitance increases degrading circuit speed
Solution Approach 1:
The patent applies curvature by forming a concave profile in the dielectric layer between adjacent fins, replacing the conventional planar structure. This concave shape reduces the overlapping area between metal gates and dielectric, thereby reducing parasitic capacitance and improving circuit speed while maintaining manufacturing feasibility through standard etching processes
2Object-affected harmful factors
If the dielectric layer thickness is increased to reduce capacitance, then parasitic capacitance decreases, but the device area and manufacturing complexity increase
Solution Approach 1:
The patent segments the dielectric layer into different regions with different profiles - a concave region between fins and planar regions elsewhere. This segmentation allows capacitance reduction in critical areas without increasing overall device area or manufacturing complexity, as the concave formation uses standard etching processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces capacitance, enhancing circuit speed and overall device performance by optimizing the structure of Fin FETs.
Implementation Method 1
performing an annealing operation to convert a portion of the one or more layers of the first dielectric layer and the insertion layer from an amorphous form to a crystalline form
Implementation Method 2
removing the remaining amorphous portion of the one or more layers of the first dielectric layer and the insertion layer to form a recess
Data Source
AI summary
A method of manufacturing a semiconductor device includes forming a fin structure including a stacked layer of first semiconductor layers and second semiconductor layers disposed over a bottom fin structure and a hard mask layer over the stacked layer, forming an isolation insulating layer so that the hard mask layer and the stacked layer are exposed from the isolation insulating layer, forming a sacrificial cladding layer over at least sidewalls of the exposed hard mask layer and stacked layer, forming layers of a first dielectric layer and an insertion layer over the sacrificial cladding layer and the fin structure, performing an annealing operation to convert a portion of the layers of the first dielectric layer and the insertion layer from an amorphous form to a crystalline form, and removing the remaining amorphous portion of the layers of the first dielectric layer and the insertion layer to form a recess.