FinFET Structure With Differential Fin Heights For Leakage Reduction
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Solution Overview
Problem
As semiconductor devices shrink, the short channel leakage effect becomes significant, leading to inadequate gate control over the channel region, particularly in conventional planar transistors, resulting in increased leakage current, which FinFETs aim to mitigate through a fin structure with a gate wrapping around three sides.
Innovation Solution
The FinFET structure features fins of varying heights for NMOS and PMOS transistors, achieved by differential ion implantation and etching processes, allowing for tuned threshold voltages and reduced leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional planar transistors are used with reduced feature size, then integration density is improved, but leakage current increases due to short channel effect
Solution Approach 1:
The patent transitions from planar transistors to FinFETs by adding vertical dimension through fin structures. The channel is formed as a vertical fin protruding from the substrate, allowing the gate to wrap around three sides of the channel, thereby improving gate control and reducing leakage current while maintaining scaled dimensions.
Solution Approach 2:
The patent segments the channel into multiple fins rather than using a single planar channel. This segmentation allows each fin to be independently controlled by the gate, improving overall gate control effectiveness and reducing short channel effects in scaled devices.
2Ease of manufacture
If uniform fin heights are used for all transistors, then fabrication is simplified, but threshold voltage control is insufficient for different transistor types
Solution Approach 1:
The patent applies different fin heights to different transistor regions (NMOS vs PMOS) based on their specific electrical requirements. Each transistor type receives a locally optimized fin height that tunes its threshold voltage appropriately, while the overall fabrication process remains relatively simple through selective etching.
Solution Approach 2:
The patent introduces asymmetric fin heights where NMOS transistors have different fin heights compared to PMOS transistors. This asymmetry enables independent optimization of threshold voltages for each transistor type, allowing better adaptation to different circuit requirements while maintaining a unified FinFET architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces leakage current by enhancing gate control over the channel region, particularly by allowing for distinct fin heights through a single etching step, thereby improving the performance of FinFETs and reducing fabrication costs.
Implementation Method 1
applying a first ion implantation process to first isolation regions in an n-type region over the substrate, depositing a second photoresist layer to cover the n-type region over the substrate, applying a second ion implantation process to second isolation regions in the p-type region
Data Source
AI summary
A method for forming FinFETs comprises forming a plurality of first fins and a plurality of second fins over a substrate and embedded in isolation regions, depositing a first photoresist layer over the substrate, removing the first photoresist layer over an n-type region, applying a first ion implantation process to the first isolation regions, wherein dopants with a first polarity type are implanted in the first isolation regions, depositing a second photoresist layer over the substrate, removing the second photoresist layer over a p-type region, applying a second ion implantation process to the second isolation regions, wherein dopants with a second polarity type are implanted in the second isolation regions, applying an annealing process to the isolation regions and recessing the first isolation regions and the second isolation regions through an etching process.