FinFET Diffusion Break with Protective Liner for Alignment
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Solution Overview
Problem
Conventional processing techniques for fin-type field effect transistors (FINFETs) face challenges in maintaining larger fin sizes for easier alignment and improving device performance, while also preventing short circuits, as smaller fins degrade performance and improper insulator size can lead to short circuits.
Innovation Solution
The use of a protective nitride liner to maintain the fin profile, allowing for a larger fin top critical dimension without affecting single diffusion breaks, and the deposition of a raise oxide at the single diffusion break region to form diffusion breaks, which helps in avoiding short circuits and improving device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the fin size is reduced to increase transistor density, then the number of transistors per unit area increases, but the device performance degrades and alignment becomes more difficult
Solution Approach 1:
The fin structure is segmented into functional regions: the top portion maintains a larger critical dimension for alignment and performance, while lower portions can be smaller to increase density. The insulator structure is also segmented with different thicknesses at different locations along the fin
Solution Approach 2:
Different regions of the fin structure are given different dimensions and properties. The top of the fin has a larger critical dimension for alignment, while the insulator thickness varies along the fin length, with thicker insulation at critical regions and thinner insulation elsewhere to maximize density
2Productivity
If the fin size is reduced to increase transistor density, then the number of transistors per unit area increases, but the alignment precision worsens
Solution Approach 1:
The fin structure is segmented into functional regions: the top portion maintains a larger critical dimension for alignment and performance, while lower portions can be smaller to increase density. The insulator structure is also segmented with different thicknesses at different locations along the fin
Solution Approach 2:
The larger fin top critical dimension is established in advance during the formation process, providing a robust alignment target before subsequent processing steps. This preliminary larger dimension makes alignment easier in later manufacturing steps
3Productivity
If the insulator size is reduced to increase transistor density, then the transistor density increases, but short circuits may occur
Solution Approach 1:
The insulator thickness is optimized locally: thicker insulator regions are placed where they are most needed for electrical isolation (such as at the base of the fin and in regions adjacent to functional transistors), while thinner insulator regions are used in areas where density is the priority and short circuit risk is lower
Solution Approach 2:
The insulator is segmented into regions of different thicknesses along the fin structure, allowing dense packing in some areas while maintaining sufficient isolation in critical regions to prevent short circuits
Data Source
AI summary
Methods form integrated circuit structures that include a semiconductor layer having at least one fin. At least three gate stacks contact, and are spaced along, the top of the fin. An insulator in trenches in the fin contacts the first and third of the gate stacks, and extends into the fin from the first and third gate stacks. Source and drain regions in the fin are adjacent a second of the gate stacks. The second gate stack is between the first and third gate stacks along the top of the fin. Additionally, a protective liner is in the trench between a top portion of the insulator a bottom portion of the insulator.