N-Type P-Type FinFET Transistor Stress Optimization
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Solution Overview
Problem
Existing semiconductor integrated circuits using the same diffusion breakdown structure for both N-type and P-type FinFET transistors fail to improve the performance of both transistor types, leading to suboptimal carrier mobility and electrical interference issues.
Innovation Solution
The integrated circuit structure configures independent diffusion breakdown structures for N-type and P-type FinFET transistors, utilizing different dielectric layers with tailored stresses and trench widths to enhance carrier mobility specifically for each type, thereby improving the performance of both N-type and P-type transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the same diffusion breakdown structure is used for both N-type and P-type FinFET transistors, then the manufacturing process is simplified, but the carrier mobility and performance of both transistor types cannot be optimized simultaneously
Solution Approach 1:
The patent applies different diffusion breakdown structures to different transistor types: a first diffusion breakdown structure with first stress is applied to N-type FinFET transistors to improve electron mobility, while a second diffusion breakdown structure with second stress is applied to P-type FinFET transistors to improve hole mobility. This local differentiation allows each transistor type to receive optimized stress conditions for its specific carrier type, resolving the contradiction between manufacturing simplicity and transistor performance.
2Reliability
If independent diffusion breakdown structures with different stresses are used for N-type and P-type FinFET transistors, then carrier mobility is enhanced, but the device complexity increases
Solution Approach 1:
The patent segments the diffusion breakdown structure into two distinct types: a first diffusion breakdown structure for N-type FinFET transistors and a second diffusion breakdown structure for P-type FinFET transistors. Each segment is independently optimized with appropriate stress characteristics matching the carrier type (electrons for N-type, holes for P-type). This segmentation enables targeted performance optimization while maintaining clear structural boundaries that simplify the overall device architecture.
3Reliability
If a diffusion breakdown structure applies stress to improve carrier mobility, then transistor performance improves, but adverse stress impact may occur on the other transistor type
Solution Approach 1:
The patent changes the stress parameter of the diffusion breakdown structure according to the transistor type: first stress is applied to N-type FinFET transistors to enhance electron mobility, while second stress (different from the first stress) is applied to P-type FinFET transistors to enhance hole mobility. This parameter differentiation ensures that each transistor type receives the optimal stress condition for its carrier type, eliminating the adverse stress impact that would occur if a single stress configuration were used for both types.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach eliminates the adverse impact of diffusion breakdown stress on transistor performance, enhancing carrier mobility and operational efficiency, particularly by optimizing electron and hole mobility in N-type and P-type FinFET transistors respectively.
Implementation Method 1
The first dielectric layer is made of a stress material to enable the first diffusion breakdown structure to have a first stress. The second dielectric layer is made of a stress material to enable the second diffusion breakdown structure to have a second stress, the second stress being different from the first stress.
Data Source
AI summary
The present application discloses an integrated circuit structure of N-type and P-type fin transistors, wherein the N-type and P-type fin transistors are respectively formed on first and second fins, first and second diffusion breakdown structures are respectively provided on the first and second fins. A first dielectric layer of the first diffusion breakdown structure is made of a stress material to enable the first diffusion breakdown structure to have a first stress. A second dielectric layer of the second diffusion breakdown structure is made of a stress material to enable the second diffusion breakdown structure to have a second stress different from the first stress. The first stress is configured according to a requirement of improving carrier mobility of a first channel area, and the second stress is configured according to a requirement of improving carrier mobility of a second channel area.