FinFET Diode Structures Using Localized Fin Density Control
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Solution Overview
Problem
The challenge in semiconductor manufacturing is to form diode and bipolar junction transistor (BJT) structures alongside FinFETs with improved electrical properties while minimizing additional manufacturing steps and maintaining compatibility with FinFET processes.
Innovation Solution
The solution involves forming diodes and BJTs using isolated fin areas and fin array areas with varying fin densities, allowing for controlled implantation depths and STI feature thicknesses without additional photomask steps, by leveraging localized etching effects and shared FinFET manufacturing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If diodes and BJTs are formed alongside FinFETs using the same manufacturing processes, then manufacturing complexity is reduced, but electrical properties of the diodes and BJTs are compromised
Solution Approach 1:
The patent applies local quality by creating isolated fin areas with different fin densities compared to the FinFET regions. The isolated fin areas have reduced fin density or contain only a single fin, which locally modifies the electrical characteristics to enable proper diode and BJT operation while maintaining high fin density in FinFET regions for optimal transistor performance. This local differentiation allows both device types to coexist on the same substrate with appropriate electrical properties.
Solution Approach 2:
The substrate is segmented into distinct regions: FinFET areas with high fin density for transistor operation, and isolated fin areas with reduced fin density for diode and BJT formation. This segmentation allows independent optimization of electrical properties in each region while using the same overall manufacturing process flow, thus resolving the contradiction between manufacturing simplicity and electrical performance.
2Reliability
If additional photomask steps are used to form diodes and BJTs with controlled implantation depths, then electrical properties are improved, but manufacturing complexity increases
Solution Approach 1:
The isolated fin areas serve themselves by providing natural depth control for dopant implantation through their reduced fin density. The etch selectivity and dopant penetration depth are self-regulated by the fin structure characteristics, eliminating the need for additional photomask steps to control implantation depths. The structure itself provides the control mechanism that would otherwise require complex process steps.
Solution Approach 2:
The patent changes the fin density parameter in isolated fin areas compared to FinFET regions. This parameter change (reduced fin density) directly controls the implantation depth and electrical characteristics without requiring additional process steps. By modifying the structural parameter (fin density) rather than adding process steps, the patent achieves both electrical performance and manufacturing simplicity.
3Manufacturing precision
If fin density is increased in isolated fin areas, then manufacturing precision is improved, but substrate noise increases
Solution Approach 1:
The patent applies local quality by reducing fin density specifically in isolated fin areas where diodes and BJTs are formed, while maintaining high fin density in FinFET regions. This local reduction in fin density decreases substrate noise generation in the isolated areas without compromising the manufacturing precision of the FinFET regions. Each region has the appropriate fin density for its specific function.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of diodes and BJTs with enhanced electrical properties and reduced manufacturing complexity, achieving desired implantation depths and minimizing substrate noise through controlled dopant distribution and STI feature management.
Implementation Method 1
etching a plurality of fins into a semiconductor substrate using the fin pattern
Implementation Method 2
implanting a p-type dopant into the fin array area and portions of the FinFET area to form p-wells, and implanting an n-type dopant into the isolated fin area
Implementation Method 3
annealing the semiconductor substrate
Data Source
AI summary
A method of forming one or more diodes in a fin field-effect transistor (FinFET) device includes forming a hardmask layer having a fin pattern, said fin pattern including an isolated fin area, a fin array area, and a FinFET area. The method further includes etching a plurality of fins into a semiconductor substrate using the fin pattern, and depositing a dielectric material over the semiconductor substrate to fill spaces between the plurality of fins. The method further includes planarizing the semiconductor substrate to expose the hardmask layer. The method further includes implanting a p-type dopant into the fin array area and portions of the FinFET area, and implanting an n-type dopant into the isolated fin area, a portion of the of fin array area surrounding the p-well and portions of the FinFET area. The method further includes annealing the semiconductor substrate.