FinFET Dipole Gate Stack for Threshold Voltage Tuning
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Solution Overview
Problem
As semiconductor technology advances, there is a challenge in maintaining switching speeds and controlling device structure dimensions in transistors, particularly with the migration from planar to FinFET technology, where the scaling down of materials leads to limitations in threshold voltage tuning and increased thickness variation, necessitating alternative materials for better performance.
Innovation Solution
The introduction of a dipole region in FinFET devices comprising an interlayer dielectric, a high-κ dielectric material, and a dipole layer made from materials like titanium lanthanum nitride (TiLaN), titanium yttrium nitride (TiYN), or hafnium-based materials, which are deposited using atomic layer deposition techniques to enhance work function capabilities and control threshold voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional materials are used in planar transistors, then manufacturing is simpler, but switching speeds deteriorate and threshold voltage control becomes difficult as device dimensions shrink
Solution Approach 1:
The patent changes the physical and chemical parameters of the gate dielectric material by transitioning from conventional silicon oxide to high-kappa materials (such as hafnium oxide, tantalum oxide, or aluminum oxide) with dielectric constants greater than 5. This parameter change enables achieving the required capacitive coupling for fast switching speeds while maintaining adequate threshold voltage control even as transistor dimensions shrink below 10 nanometers
Solution Approach 2:
The patent employs composite material structures combining high-kappa dielectric materials with metal gate electrodes (such as tungsten, titanium nitride, or tantalum nitride). This composite approach creates a metal-semiconductor field-effect transistor (MESFET) that achieves both high switching speeds through superior gate control and precise threshold voltage tuning through the combined properties of the high-kappa dielectric and metal gate layers
2Productivity
If transistor size is reduced to increase functional density, then more components fit on chip, but device structure dimension control becomes more difficult
Solution Approach 1:
The patent changes the dielectric constant parameter to high-kappa values (greater than 5), which allows the gate to maintain effective electrical control over the channel at much smaller dimensions. This enables continued scaling to increase functional density while preserving sufficient threshold voltage control through the enhanced capacitive coupling provided by the high-kappa material
Solution Approach 2:
The patent applies high-kappa dielectric materials specifically in the gate region where precise electrical control is most critical, while other portions of the transistor can use conventional materials. This localized application of advanced materials enables dimension scaling in critical areas without requiring complete material replacement throughout the entire device structure
3Manufacturing precision
If high-kappa dielectric materials are introduced, then threshold voltage control improves, but integration complexity increases
Solution Approach 1:
The patent develops high-kappa dielectric materials and metal gate combinations that can serve multiple functions simultaneously: providing high threshold voltage control, enabling fast switching speeds, and maintaining compatibility with existing CMOS fabrication processes. This multi-functionality reduces integration complexity by allowing a single material system to address multiple performance requirements rather than requiring separate specialized structures for each function
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies integration, reduces integration costs, and allows for multi-voltage tunability, enabling the shrinking of transistor sizes while maintaining device performance by providing excellent control over the dipole layer composition and reducing oxidation, thus addressing the limitations of existing materials.
Implementation Method 1
a dipole region on a top surface of the channel, the dipole region comprising an interlayer dielectric, a high-κ dielectric material, and a dipole layer
Implementation Method 2
depositing an interlayer dielectric on a top surface of a channel located between a source and a drain on a substrate; depositing a high-κ dielectric material on the interlayer dielectric; and depositing a dipole layer on the high-κ dielectric material
Data Source
AI summary
Methods of forming and processing semiconductor devices are described. Certain embodiments related to electronic devices which comprise a dipole region having an interlayer dielectric, a high-κ dielectric material, and a dipole layer. The dipole layer comprises one or more of titanium lanthanum nitride (TiLaN), titanium yttrium nitride (TiYN), titanium strontium nitride (TiSrN), titanium magnesium nitriride (TiMgN, titanium aluminum nitride (TiAlN), titanium tantalum nitride (TiTaN), hafnium carbide (HfC), hafnium nitride (HfN), hafnium oxynitride (HfON), hafnium oxycarbide (HfOC), hafnium carbide aluminum (HfCAl), hafnium aluminum nitride (HfAlN), or hafnium carbonitride (HfCN).