FinFET Anti-Punch Through Structure for Dopant Diffusion Control

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Solution Overview

Problem

FinFET transistors face performance issues due to undesirable dopants migrating from anti-punch through regions into the channel region, affecting conductivity and transistor functionality.

Innovation Solution

A layer of dielectric material is deposited on the anti-punch through regions to capture and remove unwanted dopants like fluorine and hydrogen ions through an annealing process, reducing their concentration and preventing diffusion into the channel region, while maintaining the concentration of desirable dopants.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If anti-punch through regions are doped to reduce short channel effects, then transistor reliability is improved, but undesirable dopants migrate into the channel region worsening manufacturing precision

Engineering Contradiction:
Improvetransistor reliabilityVSAvoiddopant concentration control
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

A dielectric material layer is introduced as an intermediary between the anti-punch through region and the channel region. This dielectric layer acts as a barrier that prevents undesirable dopants from migrating into the channel while allowing the anti-punch through region to maintain its dopant concentration for reliability improvement.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The structure is segmented into distinct regions with different dopant concentrations and types. The anti-punch through region contains desirable dopants for reliability, while the dielectric barrier separates it from the channel region, preventing contamination from undesirable dopants and achieving both reliability improvement and manufacturing precision.

Inventive Principle:
Principle #1Segmentation

2Reliability

If dopant concentration in anti-punch through region is increased to reduce short channel effects, then transistor performance is improved, but dopant diffusion into channel region increases worsening purity

Engineering Contradiction:
Improvetransistor performanceVSAvoiddopant diffusion
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The dielectric material layer serves as a mediator that blocks the diffusion path of undesirable dopants from the anti-punch through region into the channel region. This allows the anti-punch through region to have high dopant concentration for improved transistor performance while the dielectric barrier prevents harmful dopant diffusion.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent converts the potentially harmful effect of high dopant concentration (which could cause diffusion) into a benefit by using the dielectric barrier to contain the dopants in the anti-punch through region. The high dopant concentration becomes beneficial for reducing short channel effects without the harmful diffusion side effect.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the conductivity of the channel region, improves transistor performance by reducing leakage currents, and ensures proper functioning by minimizing the impact of unwanted dopants, resulting in improved FinFET performance.

Implementation Method 1

A layer of dielectric material is deposited on the anti-punch through regions to capture and remove unwanted dopants like fluorine and hydrogen ions through an annealing process

Methodology Applied
Scientific EffectAnnealing: Annealing

Implementation Method 2

preventing diffusion into the channel region

Methodology Applied
Scientific EffectDiffusion barrier: Diffusion Barrier

Data Source

PatentUS20240371867A1Integrated circuit with Anti-punch through control
Publication Date: 2024.11.07 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20240371867A1 patent drawing
  • US20240371867A1 patent drawing
  • US20240371867A1 patent drawing

AI summary

An integrated circuit die includes a FinFET transistor. The FinFET transistor includes an anti-punch through region below a channel region. Undesirable dopants are removed from the anti-punch through region during formation of the source and drain regions. When source and drain recesses are formed, a layer of dielectric material is deposited in the recesses. An annealing process is then performed. Undesirable dopants diffuse from the anti-punch through region into the layer of dielectric material during the annealing process. The layer of dielectric material is then removed. The source and drain regions are then formed by depositing semiconductor material in the recesses.