FinFET Bottom Portion Doped Layer for Leakage Prevention
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Solution Overview
Problem
Current FinFET fabrication methods face challenges with current leakage due to design bottlenecks in the fin-shaped structure, affecting the overall performance of the device.
Innovation Solution
A method involving the formation of doped layers and liners on the bottom portions of fin-shaped structures, followed by an annealing process to drive dopants into the substrate, forming an anti-punch-through layer to prevent current leakage, with the doped layer materials adjusted based on transistor type.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional FinFET fabrication methods are used, then the device structure is simpler and manufacturing is easier, but current leakage occurs due to insufficient isolation at the bottom portion of fin-shaped structures
Solution Approach 1:
The patent divides the fin-shaped structure into distinct top and bottom portions, applying different treatments to each. The bottom portion receives specialized doped layers and liners to prevent current leakage, while the top portion maintains the standard FinFET structure. This segmentation allows targeted improvement of reliability without unnecessarily complicating the entire device structure.
Solution Approach 2:
The patent applies local quality by introducing doped layers and liners specifically at the bottom portion of the fin-shaped structure where current leakage occurs. The doping concentration and material composition are locally optimized to provide punch-through prevention exactly where needed, rather than uniformly modifying the entire fin structure. This approach improves reliability while minimizing added complexity.
2Reliability
If doped layers and liners are added around the bottom portion of fin-shaped structures, then current leakage is reduced and isolation is enhanced, but the manufacturing process becomes more complex
Solution Approach 1:
The patent employs preliminary action by forming doped layers and liners around the bottom portion of fin-shaped structures before completing the standard FinFET fabrication process. This preliminary isolation structure is prepared in advance to prevent current leakage issues that would otherwise require complex retroactive corrections. The dopant types and concentrations are predetermined based on the transistor type (NMOS or PMOS) to streamline subsequent processing.
Solution Approach 2:
The patent utilizes parameter changes by adjusting doping concentrations, layer thicknesses, and material compositions based on the specific transistor type and performance requirements. The doped layers are formed with controlled doping concentrations to achieve optimal isolation without excessive complexity. Material parameters such as liner thickness and doping levels are tuned to balance reliability improvement with manufacturing feasibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach effectively reduces current leakage and enhances isolation, improving the performance of FinFET devices by forming an anti-punch-through layer through solid-state doping.
Implementation Method 1
an annealing process to drive dopants into the substrate, forming an anti-punch-through layer to prevent current leakage
Data Source
AI summary
A semiconductor device includes: a substrate having a first region and a second region; a first fin-shaped structure on the first region and a second fin-shaped structure on the second region, wherein each of the first fin-shaped structure and the second fin-shaped structure comprises a top portion and a bottom portion; a first doped layer around the bottom portion of the first fin-shaped structure; a second doped layer around the bottom portion of the second fin-shaped structure; a first liner on the first doped layer; and a second liner on the second doped layer.