FinFET Doped Substrate Layout for Leakage-Resistant Scaling
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Solution Overview
Problem
Existing FinFET devices and manufacturing methods have not been entirely satisfactory in addressing the complexity and scaling demands of advanced semiconductor integrated circuits, particularly in forming fin-type field-effect transistors with improved performance and reduced leakage currents.
Innovation Solution
A method for fabricating FinFET devices involving the formation of heavy and light doped regions in the substrate, with specific patterning and deposition of insulating and dielectric materials to create controlled fin structures and gate stacks, ensuring precise alignment and reduced leakage paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing FinFET manufacturing methods are used, then basic device functionality is achieved, but device performance and leakage current control are insufficient
Solution Approach 1:
The substrate is divided into multiple doped regions with different doping concentrations (first doped region, second doped region, third doped region, fourth doped region). This segmentation allows precise control of carrier concentration in different areas, improving leakage current control while maintaining manufacturing feasibility through systematic doping processes.
Solution Approach 2:
Different regions of the substrate are assigned different doping concentrations tailored to their specific functional requirements. The first and second doped regions have higher doping concentrations for source/drain contacts, while the third and fourth doped regions have lower concentrations for channel control, optimizing both performance and leakage characteristics.
2Productivity
If FinFET scaling is continued to increase functional density, then production efficiency improves, but manufacturing complexity increases
Solution Approach 1:
The patent transitions from planar transistor architecture to three-dimensional FinFET structure with vertical fins extending from the substrate. This dimensional change increases functional density by utilizing the vertical dimension for current conduction, allowing continued scaling while maintaining manufacturing process compatibility with adapted doping and deposition techniques.
Solution Approach 2:
Multiple doped regions are formed in the substrate before fin formation and device assembly. This preliminary doping action simplifies subsequent manufacturing steps by pre-establishing the electrical characteristics needed for source, drain, and channel regions, reducing overall process complexity despite the three-dimensional structure.
3Reliability
If heavy doping is applied to improve contact resistance, then electrical connectivity improves, but leakage paths increase
Solution Approach 1:
Heavy doping is applied locally only in the first and second doped regions where source and drain contacts are formed, improving electrical connectivity where needed. The third and fourth doped regions maintain lower doping concentrations to prevent leakage paths in the channel areas, achieving selective optimization of electrical properties in different locations.
Solution Approach 2:
The doping structure is segmented into multiple regions with different concentrations. The heavily doped first and second regions provide low-resistance contacts, while the lightly doped third and fourth regions maintain proper channel characteristics and prevent leakage, separating the conflicting requirements of connectivity and leakage prevention into distinct spatial zones.
Data Source
AI summary
A fin-type field-effect transistor device includes a substrate, insulators, gate stacks and dielectric strips. The substrate includes a first doped region, a second doped region, third doped blocks located above the first doped region and fourth doped blocks located above the second doped region, and fins located above the third doped blocks and the fourth doped blocks, wherein doping concentrations of the third doped blocks are lower than a doping concentration of the first doped region, and doping concentrations of the fourth doped blocks are lower than a doping concentration of the second doped region. The insulators are disposed on the third doped blocks and the fourth doped blocks of the substrate and covering the fins. The dielectric strips are disposed in between the fins, and in between the third doped blocks and the fourth doped blocks. The gate stacks are disposed over the fins and above the insulators.