FinFET Source/Drain Doping for Lower Contact Resistance
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Solution Overview
Problem
Existing FinFET devices and fabrication methods face challenges in achieving optimal performance due to issues like short channel effects and electrical interference, particularly in high-density nanometer technology process nodes.
Innovation Solution
The method involves forming a FinFET device structure with a fin structure over a substrate, using a sacrificial layer and spacers to pattern the fins, followed by the formation of a gate structure and source/drain structures with a doped region using gallium or gallium-boron to reduce contact resistance and prevent short channel effects, and forming a metal silicide layer to enhance performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional planar transistor structures are used, then fabrication is simpler, but short channel effects increase and current flow decreases
Solution Approach 1:
The patent transitions from a planar (2D) transistor structure to a three-dimensional FinFET structure with a vertical fin extending from the substrate. This dimensional change allows the gate to control the channel from three sides, significantly improving short channel effect control and current flow while maintaining fabrication feasibility through adapted processes
2Reliability
If FinFET structure is adopted, then short channel effect is reduced and current flow increases, but fabrication complexity increases
Solution Approach 1:
The fabrication process is divided into distinct sequential stages: forming the fin structure, depositing sacrificial layers, creating spacers, patterning, and final device formation. This segmentation of the complex fabrication process into manageable steps reduces overall complexity while achieving the desired FinFET structure
Solution Approach 2:
The fin structure is formed preliminarily before gate and source/drain formation. Sacrificial layers and spacers are deposited and patterned in advance to define the fin geometry, simplifying subsequent fabrication steps and reducing overall process complexity
3Ease of manufacture
If standard doping processes are used, then process simplicity is maintained, but contact resistance remains high
Solution Approach 1:
The patent introduces gallium or gallium-boron doping into the source/drain regions, changing the dopant type and concentration parameters. This specific doping approach reduces contact resistance between the metal contacts and semiconductor regions while maintaining compatibility with existing doping equipment and processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the performance of FinFET devices by reducing contact resistance and preventing short channel effects, leading to enhanced current flow and reduced leakage current, while maintaining high device density and performance.
Implementation Method 1
An outer portion of the S/D structure is doped with a dopant to form a doped region. The doped region includes gallium (Ga), or gallium (Ga)/boron (B). A metal silicide layer is formed over the doped region and in direct contact with the doped region. The doped region is configured to reduce the contact resistance between the S/D structure made of semiconductor material and the metal silicide layer made of metal layer.
Data Source
AI summary
A fin field effect transistor (FinFET) device structure is provided. The FinFET device structure includes a plurality of fin structures above a substrate, an isolation structure over the substrate and between the fin structures, and a gate structure formed over the fin structure. The FinFET device structure includes a source/drain (S/D) structure over the fin structure, and the S/D structure is adjacent to the gate structure. The FinFET device structure also includes a metal silicide layer over the S/D structure, and the metal silicide layer is in contact with the isolation structure.


