FinFET Source/Drain Doping Layout for Lower Junction Leakage
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Solution Overview
Problem
Conventional semiconductor devices with Fin structures face challenges in reducing reverse bias p-n junction leak currents and preventing excessive resistance increases in the channel region, particularly due to high concentration impurity layers formed on boundary regions.
Innovation Solution
A semiconductor device configuration that includes a channel portion, a gate electrode, and source/drain regions with semiconductor layers of a first conductivity type formed inside recessed portions on a base body, and impurity layers of a second conductivity type formed between the base body and the bottom portions of the semiconductor layers, which reduces leak current occurrence and excessive channel resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high concentration impurity layers are formed on boundary regions to reduce leak current, then leak current is reduced, but the resistance of the channel region increases excessively
Solution Approach 1:
The patent applies local quality by forming impurity layers with different conductivity types in different locations: p-type impurity layers are formed in the channel region to reduce leak current, while n-type impurity layers are formed in the source/drain regions to compensate for resistance increases. This spatial differentiation of impurity types and concentrations allows simultaneous optimization of leak current reduction and resistance control in different regions of the Fin structure.
2Reliability
If ion implantation is used for impurity profile control to reduce leak current, then leak current is reduced, but crystal defects occur in source/drain regions
Solution Approach 1:
The patent applies preliminary action by performing recrystallization treatment before forming the high concentration impurity layers. This preliminary recrystallization restores the crystal structure in the source/drain regions before subsequent ion implantation, preventing the formation of crystal defects. The sequence is critical: recrystallization first, then impurity layer formation, ensuring both leak current reduction and crystal structure integrity.
3Reliability
If halo layers are formed on etched semiconductor substrate to reduce leak current, then leak current is reduced, but high concentration impurity layers form on boundary regions causing excessive channel resistance
Solution Approach 1:
The patent applies local quality by forming impurity layers with different conductivity types in different locations: p-type impurity layers are formed in the channel region to reduce leak current, while n-type impurity layers are formed in the source/drain regions to compensate for resistance increases. This spatial differentiation of impurity types and concentrations allows simultaneous optimization of leak current reduction and resistance control in different regions of the Fin structure.
Solution Approach 2:
The patent applies asymmetry by using different conductivity types (p-type vs. n-type) and different formation methods (ion implantation vs. epitaxial growth) for impurity layers in different regions. The channel region receives p-type impurities while source/drain regions receive n-type impurities, creating an asymmetric impurity distribution that balances leak current reduction with resistance management.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution effectively reduces the occurrence of leak currents and prevents excessive resistance increases in the channel region, enhancing the performance of semiconductor devices, especially under high power supply voltages.
Implementation Method 1
impurity profile control based on ion implantation is effective
Implementation Method 2
epitaxially growing the source/drain regions on the halo layers
Data Source
AI summary
A semiconductor device according to the present disclosure includes a channel portion, a gate electrode disposed opposite the channel portion via a gate insulating film, and source/drain regions disposed at both edges of the channel portion. The source/drain regions include semiconductor layers that have a first conductivity type and that are formed inside recessed portions disposed on a base body. Impurity layers having a second conductivity type different from the first conductivity type are formed between the base body and bottom portions of the semiconductor layers.