FinFET Source/Drain Doping Layout for Leakage and Current Control
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Solution Overview
Problem
The semiconductor industry faces challenges in scaling down integrated circuits (ICs) while maintaining complexity and efficiency, particularly in processing and manufacturing three-dimensional transistors and fin-like structures.
Innovation Solution
The method involves forming non-planar semiconductor devices with fins protruding from a substrate, surrounded by isolation regions, and featuring gate dielectric layers and gate electrodes. This method includes detailed steps for forming source/drain regions, epitaxial layers, and doped layers to optimize device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If geometry size is decreased to increase functional density, then production efficiency and cost are improved, but device complexity and processing difficulty increase
Solution Approach 1:
The patent transitions from planar transistor structures to three-dimensional FinFET structures with vertical fins protruding from the substrate. This dimensional change increases the effective channel area and control gate-to-channel, enabling higher functional density while maintaining manufacturability through established lithography and etching processes adapted for vertical geometries
2Productivity
If three-dimensional transistor structures are implemented to increase functional density, then circuit capacity is improved, but processing complexity increases
Solution Approach 1:
The fabrication process is divided into distinct sequential stages: forming isolation regions, creating fins, depositing gate dielectric layers, forming gate electrodes, and creating source/drain regions. Each stage uses specialized processes optimized for that specific structural element, making the overall complex three-dimensional fabrication manageable through modular process segments
Solution Approach 2:
Isolation regions are formed beforehand to define active device areas before fin formation. The fin structures are created with precise dimensions and orientations prior to gate deposition. These preliminary actions establish the three-dimensional framework that guides subsequent processing steps, ensuring proper alignment and structural integrity throughout fabrication
Data Source
AI summary
A semiconductor structure includes a substrate and a first epitaxial source/drain feature extending into the semiconductor layer. The semiconductor structure includes a first doped region located in the semiconductor layer below the first epitaxial source/drain feature. The first doped region includes a dopant at a first concentration. The semiconductor structure includes a second epitaxial source/drain feature extending into the semiconductor layer. The semiconductor structure includes a second doped region located in the semiconductor layer below the second epitaxial source/drain feature. The second doped region includes the dopant at a second concentration that is less than the first concentration.