FinFET Source-Drain Doping Layout for Lower GIDL
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Solution Overview
Problem
Existing FinFET devices face challenges with gate induced drain leakage (GIDL) and hot carrier generation when high voltages are applied, limiting their application in high-voltage driving devices.
Innovation Solution
The method involves forming an active fin on a substrate, creating sacrificial gate patterns that intersect the active fin, and forming recess regions and source/drain regions through epitaxial growth and in-situ doping. Counter-doping is performed to decrease the carrier concentration in the source/drain regions, reducing the electric field and minimizing GIDL and hot carrier generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If high voltage is applied to FinFET devices to improve driving capability, then power and driving capability are improved, but gate induced drain leakage (GIDL) and hot carrier generation increase
Solution Approach 1:
The patent applies different doping concentrations to different regions: high carrier concentration in source regions and low carrier concentration in drain regions. This local differentiation allows the source to provide strong carrier supply for driving capability while the drain region with low carrier concentration suppresses GIDL and hot carrier generation, thus resolving the contradiction between power and harmful effects.
Solution Approach 2:
The patent changes the carrier concentration parameter spatially within the active region by forming source/drain regions with different doping levels. The drain region specifically uses low carrier concentration to reduce electric field intensity, which directly addresses the GIDL and hot carrier issues while maintaining overall device driving capability through the high-concentration source region.
2Reliability
If carrier concentration in source/drain regions is increased to improve conductivity, then electrical conductivity is improved, but electric field intensity increases leading to more GIDL and hot carrier generation
Solution Approach 1:
The patent implements local quality differentiation by assigning high carrier concentration to source regions for conductivity and low carrier concentration to drain regions for electric field control. This spatial separation allows each region to optimize its function without compromising the other, resolving the contradiction between conductivity and electric field intensity.
Solution Approach 2:
The active region is segmented into distinct source and drain regions with different carrier concentrations. The source region handles conductivity requirements while the drain region handles electric field management, dividing the functional requirements into separate zones to eliminate the trade-off.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces GIDL and hot carrier generation in FinFET devices, even when high voltages are applied, thereby enhancing the electrical characteristics and reliability of the semiconductor device.
Implementation Method 1
forming an initial source/drain region having a first carrier concentration on the recess region of the active fin by performing an epitaxial growth process
Implementation Method 2
an in-situ doping process of doping first conductivity-type impurity elements
Implementation Method 3
after the in-situ doping process is performed, counter-doping is performed using second conductivity-type impurity elements to decrease a final carrier concentration
Data Source
AI summary
A method of manufacturing a semiconductor device includes forming an active fin protruding from a substrate and extending in a first direction; forming sacrificial gate patterns intersecting the active fin and extend in a second direction; forming recess regions by etching the active fin on at least one side of each of the sacrificial gate patterns; forming source/drain regions on the recess regions; removing the sacrificial gate patterns to form openings; and forming a gate dielectric layer and a gate electrode such that gate structures are formed to cover the active fin in the openings. The source/drain regions are formed by an epitaxial growth process and an in-situ doping process of doping first conductivity-type impurity elements. In at least one of the source/drain regions, after the in-situ doping process is performed, counter-doping is performed using second conductivity-type impurity elements different from the first conductivity-type impurity elements to decrease carrier concentration.