FinFET Fin Doping Profile for Uniform Threshold Voltage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing FinFET devices face challenges in achieving uniform threshold voltage distribution along the height of the fin structure, leading to variations in on-state and off-state current densities, which affect the overall DC performance and manufacturing efficiency.
Innovation Solution
A semiconductor device structure with a uniform threshold voltage distribution is achieved by forming a fin structure with a semiconductor liner layer, a first capping layer, and a second capping layer, where the annealing process drives dopants from the liner layer into the fin structure, creating a non-uniform dopant concentration profile that compensates for factors affecting the threshold voltage, resulting in improved vertical fin profile tuning and reduced material loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a low threshold voltage is used to increase on-state current, then on-state current increases, but off-state current increases leading to high leakage
Solution Approach 1:
The patent applies local quality by creating different dopant concentrations at different heights of the fin structure. The liner layer provides a first dopant concentration at the bottom portion while the upper portion has a second dopant concentration, allowing different regions to have optimized characteristics for their specific functions - high threshold voltage at the bottom to prevent leakage and low threshold voltage at the top to enable high on-state current.
2Reliability
If the gate contacts three surfaces at the top region, then gate control is improved, but threshold voltage becomes non-uniform along the fin height
Solution Approach 1:
The patent compensates for the non-uniform threshold voltage caused by the multi-surface gate contact by implementing local quality variations through the liner layer. The different dopant concentrations at different heights create local threshold voltage adjustments that counterbalance the effects of the gate contacting three surfaces at the top, thereby achieving uniform overall threshold voltage distribution.
3Ease of manufacture
If the fin has non-uniform shape and width along its height, then fabrication is simplified, but threshold voltage distribution becomes non-uniform
Solution Approach 1:
The patent changes the dopant concentration parameter along the height of the fin structure to compensate for the non-uniform geometry. By varying the dopant concentration in the liner layer at different heights, the threshold voltage is adjusted to maintain uniformity despite the fin's non-uniform shape and width, thus preserving manufacturing precision while allowing fabrication simplicity.
4Reliability
If anti-punch-through dopants are distributed non-uniformly, then punch-through is prevented, but threshold voltage distribution becomes non-uniform
Solution Approach 1:
The patent uses local quality by implementing a height-dependent dopant concentration profile in the liner layer. The dopant concentration is higher at the bottom portion where punch-through prevention is critical and lower at the upper portion, thereby simultaneously achieving punch-through protection and uniform threshold voltage distribution through spatially varying dopant characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution ensures better DC performance by reducing variations in current densities and minimizing fin top loss during manufacturing, leading to enhanced semiconductor device performance and efficiency.
Implementation Method 1
the annealing process drives dopants from the liner layer into the fin structure, creating a non-uniform dopant concentration profile
Data Source
AI summary
An embodiment method includes: forming a semiconductor liner layer on exposed surfaces of a fin structure that extends above a dielectric isolation structure disposed over a substrate; forming a first capping layer to laterally surround a bottom portion of the semiconductor liner layer; forming a second capping layer over an upper portion of the semiconductor liner layer; and annealing the fin structure having the semiconductor liner layer, the first capping layer, and the second capping layer thereon, the annealing driving a dopant from the semiconductor liner layer into the fin structure, wherein a dopant concentration profile in a bottom portion of the fin structure is different from a dopant concentration profile in an upper portion of the fin structure.